CN1344424A - 不满填充受控折叠芯片连接(c4)集成电路封装的生产流水线 - Google Patents

不满填充受控折叠芯片连接(c4)集成电路封装的生产流水线 Download PDF

Info

Publication number
CN1344424A
CN1344424A CN00804565A CN00804565A CN1344424A CN 1344424 A CN1344424 A CN 1344424A CN 00804565 A CN00804565 A CN 00804565A CN 00804565 A CN00804565 A CN 00804565A CN 1344424 A CN1344424 A CN 1344424A
Authority
CN
China
Prior art keywords
discontented
packing material
substrate
integrated circuit
suprabasil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN00804565A
Other languages
English (en)
Other versions
CN1171296C (zh
Inventor
D·库克
S·拉马林加姆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1344424A publication Critical patent/CN1344424A/zh
Application granted granted Critical
Publication of CN1171296C publication Critical patent/CN1171296C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909Post-treatment of the layer connector or bonding area
    • H01L2224/83951Forming additional members, e.g. for reinforcing, fillet sealant
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种不满填充安装在基底上的集成电路的高吞吐量生产流水线和方法。生产流水线包括一个将单一不满填充材料发放到基底上的第一发放站和一个烘箱,烘箱在不满填充材料在集成电路和基底之间流动期间移动基底。生产流水线消除了作为获得高吞吐量瓶颈的流动时间(毛细作用时间)。

Description

不满填充受控折叠芯片连接(C4) 集成电路封装的生产流水线
                     发明背景
1.发明领域
本发明涉及一种集成电路封装。
2.背景信息
集成电路典型是装入焊接在印刷电路板上的封装之中。图1给出了一种通常称为倒焊法或C4封装的集成电路封装。集成电路1包含很多焊在基底3上表面上的焊接突起2。
基底3典型是由复合材料构成,其热膨胀系数与集成电路的热膨胀系数不同。封装温度的任何变化都会引起集成电路1和基底3之间的不均匀膨胀。不均匀膨胀会产生可能使焊接突起破裂的压力。焊接突起2在集成电路1和基底3之间传导电流,因此焊接突起2中的任何裂痕都会影响电路1的运行。
封装包括位于集成电路1和基底3之间的不满填充材料4。不满填充材料4典型是环氧,它加强了IC封装焊点的可靠性和热机械水分稳定性。
封装可以包括数百个焊接突起2,排列成二维阵列穿过集成电路1的底部。环氧4典型是通过沿着集成电路的一边发放单行未固化环氧材料而用在焊接突起接触面的。然后环氧在焊接突起之间流动。环氧4必须以覆盖所有焊接突起2的方式发放。
最好是只在集成电路的一面发放环氧4以确保在不满填充中不形成气孔。气孔减弱了集成电路/基底接触面的结构完整性。另外,不满填充材料4与基底3和集成电路1两者必须具有良好的粘合强度以防止在热填充和水分填充期间分层。因此环氧4必须是以这样一种状态提供的材料,它能够在整个集成电路/基底接触面下流动,同时具有良好的粘性。
基底3典型由陶瓷材料构成。陶瓷材料大量制造相对要比较昂贵。因此想要为C4封装提供一种有机基底。有机基底会吸收不满填充过程中释放出的水分。不满填充过程中释放出的水分会在不满填充材料中产生砂眼。与陶瓷基底相比,有机基底还具有较高的热膨胀系数,会在管芯、不满填充材料和焊接突起中产生较高的压力。环氧中较高的压力会在热填充期间产生延伸到基底之中的裂痕,并使金属痕迹破裂而导致封装失败。在热填充期间较高的压力还会导致管芯失败,增加对气孔和水泡的灵敏度。突起在热填充期间可能会挤压出砂眼,特别是对于具有相对较高突起密度的封装。我们要做的事是提供一种使用有机基底的C4封装。
                        发明简述
本发明的一个实施方案是不满填充安装在基底上的集成电路的生产流水线。流水线包括将第一不满填充材料发放到基底上的第一发放站和一个烘箱,它在不满填充材料在集成电路和基底之间流动期间移动基底。
                        附图简述
图1是现有技术的集成电路封装侧视图;
图2是本发明集成电路封装的一个实施方案顶视图;
图3是放大的集成电路封装侧视图。
图4是一个示意图,显示了装配集成电路封装的方法。
                         发明详述
参考附图,尤其是参考标号,图2和图3给出了本发明集成电路封装10的一个实施方案。封装10包括基底12,基底包括第一表面14和与其相对的第二表面16。集成电路18可以通过多个焊接突起20连接到基底12的第一表面14。焊接突起20排列成二维阵列穿过集成电路18。焊接突起20可以使用通常称为受控折叠芯片连接(C4)的方法连接到集成电路18和基底12。
焊接突起20传导集成电路18和基底12之间的电流。基底12的一个实施方案包括一种有机绝缘材料。封装10有很多焊接球,连接到基底12的第二表面16。焊接球22可以回流以将封装10连接到印刷电路板(没有给出)。
基底12可以包括路线痕迹、电源/地平面、通路等等,将第一表面14的焊接突起20电连接到第二表面16上的焊接球。集成电路18可以由密封材料密封起来(没有给出)。另外,封装10可以加上一个热铁芯或热槽之类的热元件(没有给出)来去除集成电路18产生的热量。
封装10包括连接到集成电路18和基底12的第一不满填充材料24。封装10还包括连接基底12和集成电路18的第二不满填充材料26。第二不满填充材料26形成一个环带,环绕和密封IC和第一不满填充材料24的边缘。第二材料26的密封功能会防止水分移动、集成电路破裂和第一不满填充材料的裂缝。
第一不满填充材料24可以是日本Shin-Itsu生产的、产品标号为Semicoat5230-JP的环氧。Semicoat5230-JP材料提供了良好的流动性和粘性。第二不满填充材料26可以是日本Shin-Itsu生产的、产品标号为Semicoat122X的酸酐环氧。Semicoat122X材料的粘性低于Semicoat5230-JP,但抗断裂/破裂要好得多。
图4给出了一个装配封装10的方法。基底12一开始要在步骤1中在烘箱里烘烤以去掉基底材料中的水分。基底12烘烤温度最好要高于余下不满填充处理步骤的处理温度,确保在随后的步骤中基底12不会释放出水分。举例来说,基底12可以在163℃上烘烤。
在烘烤过程之后,集成电路18被安装在基地12上。集成电路18典型是通过回流焊接突起20来安装。
在第一发放站30中,第一不满填充材料24沿着集成电路的一边发放到基底12上。第一不满填充材料24在毛细作用下于集成电路18和基底12之间流动。举例来说,第一不满填充材料24可以在110~120℃的温度下发放。完全填充集成电路18和基底12之间的空隙要经过一系列发放的步骤。
封装10要自始至终在烘炉32中移动以完成第一不满填充材料24的完全流动和部分胶凝。举例来说,在烘箱32里要将不满填充材料24加热到120~145℃的温度才能使其部分胶凝。部分胶凝会减少砂眼形成,增强集成电路18和不满填充材料24之间的黏连。黏连的增强会减少水分移动、不满填充材料24和IC18之间的分层以及不满填充材料24和基底12之间的分层。砂眼形成减少了会降低热填充期间突起挤出的可能性。在毛细处理期间,封装要自始至终在加热不满填充材料的烘箱中不停的移动。在毛细处理期间不停移动基底12降低了不满填充集成电路所需的时间,从而减少了生产封装的成本。基底可以在传送带(没有给出)上在发放站30和34之间移动,并穿过烘箱32。
在第二发放站34,第二不满填充材料26沿着集成电路18的所有四个边发放到基底上。第二不满填充材料26以生成一个环绕并密封第一材料24的填充带的方式来发放。举例来说,第二材料26在大约80~120℃的温度下发放。
第一不满填充材料24和第二不满填充材料26会固化为坚硬的状态。材料在大约150℃的温度下固化。在不满填充材料24和26固化之后,焊接球22被加在基底12的第二表面16上。
虽然已经讲述并在附图中给出了具有一定代表性的实施方案,但这可理解为这样的实施方案只是示意性的,不是对概括性的发明加以限制,本发明不只限于给出的和讲述的特定结构与排列,所以那些普通的技术人员可以进行其它不同的修改。

Claims (18)

1.一种不满填充安装在基底上的集成电路的生产流水线,包括:
第一发放站,可以将第一不满填充材料发放到基底上;以及
一个加热第一不满填充材料的烘箱,该烘箱在第一不满填充材料在集成电路和基底之间流动时移动该基底。
2.如权利要求1所述的生产流水线,还包括将第二不满填充材料发放到基底上的第二发放站。
3.如权利要求1所述的生产流水线,其中第二不满填充材料密封第一不满填充材料。
4.如权利要求1所述的生产流水线,其中第一不满填充材料是环氧的。
5.如权利要求4所述的生产流水线,其中第二不满填充材料是酸酐环氧。
6.如权利要求1所述的生产流水线,其中烘箱将第一不满填充材料加热到部分胶凝状态。
7.一种不满填充安装到基底上的集成电路的方法,包括:
将第一不满填充材料发放到基底上;以及
加热第一不满填充材料,同时移动基底穿过烘箱。
8.如权利要求7所述的方法,其中第一不满填充材料在集成电路和基底之间流动。
9.如权利要求8所述的方法,还包括环绕第一不满填充材料发放第二不满填充材料的步骤。
10.如权利要求7所述的方法,还包括在发放第一不满填充材料之前加热基底的步骤。
11.如权利要求10所述的方法,其中加热基底的温度要高于第一不满填充材料移过烘箱的温度。
12.如权利要求7所述的方法,还包括使用焊接突起将集成电路安装到基底上的步骤。
13.如权利要求12所述的方法,还包括将焊接球加在基底上的步骤。
14.一个不满填充安装在基底上的集成电路的方法,包括:
将第一不满填充材料发放到基底上;以及
在第一不满填充材料在集成电路和基底之间流动期间移动基底。
15.如权利要求14所述的方法,还包括环绕第一不满填充材料发放第二不满填充材料的步骤。
16.如权利要求14所述的方法,还包括在第一不满填充材料发放之前加热基底的步骤。
17.如权利要求14所述的方法,还包括使用焊接突起将集成电路安装在基底上的步骤。
18.如权利要求17所述的方法,还包括将焊接球附到基底上的步骤。
CNB008045658A 1999-03-03 2000-02-08 不满填充受控折叠芯片连接(c4)集成电路封装的生产流水线 Expired - Fee Related CN1171296C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/262,132 1999-03-03
US09/262,132 US6528345B1 (en) 1999-03-03 1999-03-03 Process line for underfilling a controlled collapse

Publications (2)

Publication Number Publication Date
CN1344424A true CN1344424A (zh) 2002-04-10
CN1171296C CN1171296C (zh) 2004-10-13

Family

ID=22996282

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB008045658A Expired - Fee Related CN1171296C (zh) 1999-03-03 2000-02-08 不满填充受控折叠芯片连接(c4)集成电路封装的生产流水线

Country Status (7)

Country Link
US (1) US6528345B1 (zh)
JP (1) JP2002538624A (zh)
KR (1) KR100438991B1 (zh)
CN (1) CN1171296C (zh)
AU (1) AU2986100A (zh)
MX (1) MXPA01008581A (zh)
WO (1) WO2000052751A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6833629B2 (en) * 2001-12-14 2004-12-21 National Starch And Chemical Investment Holding Corporation Dual cure B-stageable underfill for wafer level
US7238550B2 (en) * 2002-02-26 2007-07-03 Tandon Group Ltd. Methods and apparatus for fabricating Chip-on-Board modules
US6798806B1 (en) * 2002-09-03 2004-09-28 Finisar Corporation Hybrid mirror VCSELs
US7026376B2 (en) * 2003-06-30 2006-04-11 Intel Corporation Fluxing agent for underfill materials
US7242097B2 (en) 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
US20050121310A1 (en) * 2003-12-03 2005-06-09 Intel Corporation Method and substrate to control flow of underfill
JP5262045B2 (ja) * 2007-09-27 2013-08-14 富士通セミコンダクター株式会社 電極の形成方法及び半導体装置の製造方法
US7915732B2 (en) * 2008-06-30 2011-03-29 International Business Mahines Corporation Production of integrated circuit chip packages prohibiting formation of micro solder balls

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4322737A (en) 1979-11-20 1982-03-30 Intel Corporation Integrated circuit micropackaging
JPS63239827A (ja) 1987-03-27 1988-10-05 Hitachi Ltd 半導体装置
EP0340492A3 (en) * 1988-05-02 1990-07-04 International Business Machines Corporation Conformal sealing and interplanar encapsulation of electronic device structures
JPH0256941A (ja) 1988-08-20 1990-02-26 Matsushita Electric Works Ltd 半導体素子の封止方法
JPH0340458A (ja) 1989-07-07 1991-02-21 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JPH0639563B2 (ja) 1989-12-15 1994-05-25 株式会社日立製作所 半導体装置の製法
US5371325A (en) 1992-10-30 1994-12-06 At&T Corp. Insulation system for magnetic devices
US5321583A (en) 1992-12-02 1994-06-14 Intel Corporation Electrically conductive interposer and array package concept for interconnecting to a circuit board
US5371328A (en) 1993-08-20 1994-12-06 International Business Machines Corporation Component rework
JP2774436B2 (ja) 1993-09-07 1998-07-09 リンナイ株式会社 多孔質体
US5539153A (en) 1994-08-08 1996-07-23 Hewlett-Packard Company Method of bumping substrates by contained paste deposition
JP3233535B2 (ja) 1994-08-15 2001-11-26 株式会社東芝 半導体装置及びその製造方法
JPH08153830A (ja) 1994-11-29 1996-06-11 Toshiba Corp 半導体装置およびその製造方法
US5864178A (en) 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
US5811317A (en) 1995-08-25 1998-09-22 Texas Instruments Incorporated Process for reflow bonding a semiconductor die to a substrate and the product produced by the product
EP0778616A3 (en) 1995-12-05 1999-03-31 Lucent Technologies Inc. Method of packaging devices with a gel medium confined by a rim member
US5766982A (en) 1996-03-07 1998-06-16 Micron Technology, Inc. Method and apparatus for underfill of bumped or raised die
JP3235454B2 (ja) 1996-03-29 2001-12-04 松下電器産業株式会社 電子部品の接合方法
US5751556A (en) 1996-03-29 1998-05-12 Intel Corporation Method and apparatus for reducing warpage of an assembly substrate
US5821456A (en) 1996-05-01 1998-10-13 Motorola, Inc. Microelectronic assembly including a decomposable encapsulant, and method for forming and reworking same
JP2891184B2 (ja) * 1996-06-13 1999-05-17 日本電気株式会社 半導体装置及びその製造方法
JPH1055832A (ja) 1996-08-08 1998-02-24 Yazaki Corp 圧接端子
US5804771A (en) 1996-09-26 1998-09-08 Intel Corporation Organic substrate (PCB) slip plane "stress deflector" for flip chip deivces
JP2848357B2 (ja) 1996-10-02 1999-01-20 日本電気株式会社 半導体装置の実装方法およびその実装構造
US5942805A (en) 1996-12-20 1999-08-24 Intel Corporation Fiducial for aligning an integrated circuit die
US5891753A (en) 1997-01-24 1999-04-06 Micron Technology, Inc. Method and apparatus for packaging flip chip bare die on printed circuit boards
US5990552A (en) 1997-02-07 1999-11-23 Intel Corporation Apparatus for attaching a heat sink to the back side of a flip chip package
US5815372A (en) 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US6104093A (en) 1997-04-24 2000-08-15 International Business Machines Corporation Thermally enhanced and mechanically balanced flip chip package and method of forming
JPH1154884A (ja) 1997-08-06 1999-02-26 Nec Corp 半導体装置の実装構造
US5919329A (en) 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6049122A (en) 1997-10-16 2000-04-11 Fujitsu Limited Flip chip mounting substrate with resin filled between substrate and semiconductor chip
US5998242A (en) 1997-10-27 1999-12-07 Lsi Logic Corporation Vacuum assisted underfill process and apparatus for semiconductor package fabrication
US5917702A (en) 1997-11-26 1999-06-29 Intel Corporation Corner heat sink which encloses an integrated circuit of a ball grid array integrated circuit package
US6049124A (en) 1997-12-10 2000-04-11 Intel Corporation Semiconductor package
US5936304A (en) 1997-12-10 1999-08-10 Intel Corporation C4 package die backside coating
US5965937A (en) 1997-12-15 1999-10-12 Intel Corporation Thermal interface attach mechanism for electrical packages
US5920120A (en) 1997-12-19 1999-07-06 Intel Corporation Assembly for dissipatating heat from a semiconductor chip wherein a stress on the semiconductor chip due to a thermally conductive member is partially relieved
US5991161A (en) 1997-12-19 1999-11-23 Intel Corporation Multi-chip land grid array carrier
US6201301B1 (en) 1998-01-21 2001-03-13 Lsi Logic Corporation Low cost thermally enhanced flip chip BGA
US5953814A (en) * 1998-02-27 1999-09-21 Delco Electronics Corp. Process for producing flip chip circuit board assembly exhibiting enhanced reliability
US6057381A (en) * 1998-07-02 2000-05-02 National Starch And Chemical Investment Holding Corporation Method of making an electronic component using reworkable underfill encapsulants
US6238948B1 (en) 1999-03-03 2001-05-29 Intel Corporation Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material

Also Published As

Publication number Publication date
US6528345B1 (en) 2003-03-04
CN1171296C (zh) 2004-10-13
KR100438991B1 (ko) 2004-07-02
WO2000052751A1 (en) 2000-09-08
KR20020005612A (ko) 2002-01-17
AU2986100A (en) 2000-09-21
JP2002538624A (ja) 2002-11-12
MXPA01008581A (es) 2002-04-24

Similar Documents

Publication Publication Date Title
US20070235217A1 (en) Devices with microjetted polymer standoffs
CN1165979C (zh) 集成电路封装方法
US20150318228A1 (en) Module and method for producing module
US5414928A (en) Method of making an electronic package assembly with protective encapsulant material
CN102593020B (zh) 制造半导体设备的方法、半导体设备以及使用该半导体设备的点火器
KR19990006293A (ko) 플립칩과 볼 그리드 어레이 (bga)를 상호 접속시키는 방법
CN1171296C (zh) 不满填充受控折叠芯片连接(c4)集成电路封装的生产流水线
CN101853835B (zh) 倒装芯片封装的制造方法
CN1157782C (zh) 利用加热到部分凝胶态的底层填料底层填充控制熔塌芯片连接(c4)集成电路封装的方法
US20020014688A1 (en) Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
KR100748558B1 (ko) 칩 사이즈 패키지 및 그 제조 방법
JP3309832B2 (ja) 電子部品の接続構造及び接続方法
CN114980552A (zh) 表面贴装芯片及其点胶填充方法
JP4324773B2 (ja) 半導体装置の製造方法
JPH1098077A (ja) 半導体装置の製造方法
KR100498675B1 (ko) 두 가지 다른 하부 충전 재료를 갖는 붕괴 제어형 칩접속(c4) 집적회로 패키지
JPH11340278A (ja) 半導体装置実装用樹脂シート及びフリップチップ実装方法並びに回路基板
JP4117480B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP2005340451A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
CN115810547A (zh) 使用间隔件进行底部填充的方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20041013

Termination date: 20150208

EXPY Termination of patent right or utility model