JP4556788B2 - 多段電子部品の製造方法 - Google Patents
多段電子部品の製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 44
- 239000000758 substrate Substances 0.000 claims description 142
- 229920005989 resin Polymers 0.000 claims description 83
- 239000011347 resin Substances 0.000 claims description 83
- 238000000034 method Methods 0.000 claims description 13
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000005476 soldering Methods 0.000 claims description 4
- 239000011800 void material Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 11
- 238000007789 sealing Methods 0.000 description 7
- 238000002844 melting Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000005192 partition Methods 0.000 description 4
- 238000007689 inspection Methods 0.000 description 3
- 238000005304 joining Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
以下、本発明の実施の形態1について説明する。図1は本発明の実施の形態1における多段電子部品の製造方法により製造される多段電子部品の斜視図、図2は本発明の実施の形態1における多段電子部品の製造方法により製造される多段電子部品の側断面図、図3は本発明の実施の形態1における多数個取り基板の斜視図、図4は本発明の実施の形態1における多段電子部品の製造工程の説明図である。
面に形成された電極6aが接合されている。チップ6の下面と主基板2の上面の間には樹脂7が充填され、電極6aと電極2bの接合を補強するとともにチップ6の能動面を封止している。電極2a、2b、2cは主基板2内において所定の配線パターン2dにより電気的に接続されている。
ように、多数個取り基板12の上面で流動して空隙部aに進入する。さらに、狭小な空隙部aとの接触部に生じる毛管現象によって空隙部aの内奥までに進入し、これを完全に充填する。
次に、本発明の実施の形態2について、図5を参照して説明する。図5(a)〜(e)は、本発明の実施の形態2における多段電子部品の製造方法を工程順に示している。なお、以下の説明において、実施の形態1と同一の工程については説明を省略する。
次に、本発明の実施の形態3について、図6を参照して説明する。図6(a)〜(d)は、本発明の実施の形態3における多段電子部品の製造方法を工程順に示している。実施の形態3における多段電子部品の製造方法は、実施の形態1における多段電子部品の製造方法に、図6(a)に示すように、第2の電子部品3上に更に第2の電子部品3を搭載する工程が付加される。バンプ9を加熱して溶融させる工程は、最上段の第2の電子部品3を搭載した後に1回だけ行なうのが好ましいが、各段の第2の電子部品3を搭載する度に行うようにしてもよい。図6(b)において、多数個取り基板12の上面であって第2の電子部品3の縁部の側方に塗布されるアンダーフィル樹脂4は、上記の空隙部aに加え中段の第2の電子部品3の主基板8と上段の第2の電子部品3の主基板8の間の空隙部eを充填する必要があるので、実施の形態1におけるアンダーフィル樹脂4の塗布量の2倍程度の量を塗布する必要がある。
次に、本発明の実施の形態4について、図7を参照して説明する。図7(a)〜(d)は、本発明の実施の形態4における多段電子部品の製造方法を工程順に示している。実施の形態4における多段電子部品の製造方法は、実施の形態2における多段電子部品の製造
方法に、図7(a)に示すように、チップ10の上面を含む第2の電子部品3上に更に先塗り型の樹脂20を塗布し、図7(b)に示すように、先塗り型の樹脂20が塗布された第2の電子部品3上に更に第2の電子部品3を実装する工程が付加される。これにより、図7(c)に示すように、主基板2と中段の第2の電子部品3の間c及び中段の第2の電子部品3と上段の第2の電子部品3の間fと主基板8の縁部の側方dが先塗り型の樹脂20により樹脂封止される。
2 主基板
3 第2の電子部品
4 アンダーフィル樹脂
5、9 バンプ
6、10 チップ
8 主基板
12 多数個取り基板
20 先塗り型の樹脂
Claims (3)
- 主基板上にチップを実装した第1の電子部品上に、主基板上にチップを実装し、前記主基板の下面に半田により形成されたバンプを備えた第2の電子部品を少なくとも一つ電気的に接続させて段積みしてなる多段電子部品の製造方法であって、
前記第1の電子部品を構成する主基板を複数個連結してなり、これらの主基板上にチップが実装された多数個取り基板を準備し、
前記第1の電子部品を構成する主基板上に第2の電子部品を搭載し、前記バンプを溶融させ、前記第1の電子部品と前記第2の電子部品を電気的に接合させる工程と、
前記多数個取り基板の上面であって前記第2の電子部品の主基板の縁部の側方に樹脂を塗布する工程と、
前記第1の電子部品を構成する主基板と前記第2の電子部品の主基板の間の空隙部を充填した樹脂を硬化させる工程と、
前記多数個取り基板を裁断して前記第1の電子部品を構成する主基板毎に分割する工程と、
を含むことを特徴とする多段電子部品の製造方法。 - 主基板上にチップを実装した第1の電子部品上に、主基板上にチップを実装し、前記主基板の下面に半田により形成されたバンプを備えた第2の電子部品を少なくとも一つ電気的に接続させて段積みしてなる多段電子部品の製造方法であって、
前記第1の電子部品を構成する主基板を複数個連結してなり、それぞれの主基板上にチップを実装した多数個取り基板を準備し、
前記第1の電子部品を構成する主基板上に第2の電子部品を搭載し、前記バンプを溶融させ、前記第1の電子部品と前記第2の電子部品を電気的に接合させる工程と、
前記多数個取り基板の上面であって前記第2の電子部品の主基板の縁部の側方に樹脂を塗布する工程と、
この樹脂を前記第1の電子部品を構成する主基板と前記第2の電子部品の主基板の間の空隙部に進入させる工程と、
前記空隙部に進入してこれを充填した前記樹脂を硬化させる工程と、
前記多数個取り基板を裁断して前記第1の電子部品を構成する主基板毎に分割する工程と、
を含むことを特徴とする多段電子部品の製造方法。 - 主基板上にチップを実装した第1の電子部品上に、主基板上にチップを実装し、前記主基板の下面に半田により形成されたバンプを備えた第2の電子部品を少なくとも一つ電気的に接続させて段積みしてなる多段電子部品の製造方法であって、
前記第1の電子部品を構成する主基板を複数個連結してなり、それぞれの主基板上にチップを実装した多数個取り基板を準備し、
前記第1の電子部品を構成する主基板の上面に樹脂を塗布する工程と、
前記第1の電子部品を構成する主基板の上面に塗布された樹脂上に第2の電子部品を搭載する工程と、
前記第2の電子部品を搭載した多数個取り基板を加熱することにより前記樹脂を硬化させるとともに、前記バンプを溶融させ、前記第1の電子部品と前記第2の電子部品を電気的に接合させる工程と、
前記多数個取り基板を裁断して前記第1の電子部品を構成する主基板毎に分割する工程と、
を含むことを特徴とする多段電子部品の製造方法。
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2002203874A (ja) * | 2000-12-28 | 2002-07-19 | Toray Eng Co Ltd | チップの実装方法 |
JP2002237496A (ja) * | 2001-02-08 | 2002-08-23 | Mitsubishi Electric Corp | 半導体装置の製造装置およびこれを用いた半導体装置の製造方法 |
JP2003303922A (ja) * | 2002-04-11 | 2003-10-24 | Hitachi Chem Co Ltd | 半導体パッケージ用基板、これを用いた半導体パッケージとその積層体、およびこれらの製造方法 |
JP2003332381A (ja) * | 2002-05-14 | 2003-11-21 | Misuzu Kogyo:Kk | 電子部品の実装方法 |
JP2004228323A (ja) * | 2003-01-22 | 2004-08-12 | Renesas Technology Corp | 半導体装置 |
JP2004327856A (ja) * | 2003-04-25 | 2004-11-18 | North:Kk | 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法 |
JP2005045284A (ja) * | 2001-03-26 | 2005-02-17 | Denso Corp | 電子部品の実装方法 |
JP2006319243A (ja) * | 2005-05-16 | 2006-11-24 | Elpida Memory Inc | メモリモジュールおよびその製造方法 |
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JP2002203874A (ja) * | 2000-12-28 | 2002-07-19 | Toray Eng Co Ltd | チップの実装方法 |
JP2002237496A (ja) * | 2001-02-08 | 2002-08-23 | Mitsubishi Electric Corp | 半導体装置の製造装置およびこれを用いた半導体装置の製造方法 |
JP2005045284A (ja) * | 2001-03-26 | 2005-02-17 | Denso Corp | 電子部品の実装方法 |
JP2003303922A (ja) * | 2002-04-11 | 2003-10-24 | Hitachi Chem Co Ltd | 半導体パッケージ用基板、これを用いた半導体パッケージとその積層体、およびこれらの製造方法 |
JP2003332381A (ja) * | 2002-05-14 | 2003-11-21 | Misuzu Kogyo:Kk | 電子部品の実装方法 |
JP2004228323A (ja) * | 2003-01-22 | 2004-08-12 | Renesas Technology Corp | 半導体装置 |
JP2004327856A (ja) * | 2003-04-25 | 2004-11-18 | North:Kk | 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法 |
JP2006319243A (ja) * | 2005-05-16 | 2006-11-24 | Elpida Memory Inc | メモリモジュールおよびその製造方法 |
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