JPH09172038A - 半導体素子の基板上接着連結構造 - Google Patents

半導体素子の基板上接着連結構造

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Publication number
JPH09172038A
JPH09172038A JP8003453A JP345396A JPH09172038A JP H09172038 A JPH09172038 A JP H09172038A JP 8003453 A JP8003453 A JP 8003453A JP 345396 A JP345396 A JP 345396A JP H09172038 A JPH09172038 A JP H09172038A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor chip
material layer
printed circuit
balls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8003453A
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English (en)
Inventor
Dae Soon Kang
大淳 姜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
LG Semicon Co Ltd
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Filing date
Publication date
Application filed by LG Semicon Co Ltd filed Critical LG Semicon Co Ltd
Publication of JPH09172038A publication Critical patent/JPH09172038A/ja
Pending legal-status Critical Current

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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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Abstract

(57)【要約】 (修正有) 【課題】半導体チップと印刷回路基板との界面接着力を
増大し得る半導体素子の基板上接着連結構造を提供す
る。 【解決手段】複数個のソルダボール16が付着された半
導体チップ18と、該半導体チップと基板13上面に接
着され複数個のホール15が穿孔形成された下部充填物
質層14と、から半導体素子の基板上接着連結構造が形
成されている。

Description

【発明の詳細な説明】
【0001】
【発明の属する技術分野】本発明は、基板に半導体素子
を接着するときの連結構造に係り、特に、支持ボード
(supporting board)叉は基板(substrate)上に半導
体素子を接着して連結するときのボンディング及び下部
充填(under fill)の作業過程を同時に行い得る半導体
素子の基板上接着連結構造に関するものである。
【0002】
【従来の技術】従来基板上に半導体素子を接着するとき
連結構造においては、図4(A)に示すように、半導体
チップ1と、該半導体チップ1の下方に形成された複数
個のソルダボール2(solder ball)(バンプに代替可
能)と、前記半導体チップと印刷回路基板3間のソルダ
ボール2の外周に形成された下部充填領域4と、から構
成されていた。
【0003】このような半導体素子の基板上接着連結構
造置は、印刷回路基板3上の半導体チップ1を加熱叉は
圧着の方式によりボンディングし、図4(B)に示すよ
うに、下部充填領域4にノズル7を用いて高分子化合物
(EMC;Epoxy molding Compound)(図示せず)を
注射し、該高分子化合物を前記下部充填領域4に流れ込
まして充填させ、フリップチップパッケージ(flip chi
p package) 叉はチップスケールパッケージ(Chip Sca
le Package)を構成していた。
【0004】
【発明が解決しようとする課題】然るに、このような従
来半導体素子の基板上接着連結構造は、半導体チップと
印刷回路基板との間に高分子化合物を強制に、叉は重力
を用いて注入させて構成されるため、半導体チップと印
刷回路基板との間に注入された物質の気泡を除去するこ
とが難しく、下部充填物質及びソルダ(バンプ)の亀裂
が発生し、半導体チップと印刷回路基板との間に注入さ
れた下部充填領域4の物質が長い間接着力を維持し得な
くなって製品の信頼性が低下し、ソルダボール(バン
プ)の短絡に係る不良品が発生するという問題点があっ
た。
【0005】且つ、別途の下部充填工程のため全体工程
を行うようになるので、全体の工程が煩雑になり、製造
原価の上昇及び生産性が低下するという問題点があっ
た。
【0006】それで、本発明の目的は、下部充填物質を
塗布し圧着して半導体チップと印刷回路基板との界面接
着力を増大し得る、半導体素子の基板上接着連結構造を
提供しようとするものである。
【0007】
【課題を解決するための手段】そして、このような目的
を達成するため本発明は、複数個のソルダボールの付着
された半導体チップと、該半導体チップと基板上面間に
接着され複数個のホールが穿孔形成された下部充填物質
層と、から半導体素子の基板上接着連結構造を形成す
る。
【0008】
【発明の実施の形態】以下、本発明の実施例に対し図面
を用いて詳細に説明する。
【0009】先ず、図1(A)に示すように、印刷回路
基板13の上面には平らな下部充填物質層14と、複数
のソルダボール16の付着された半導体チップ18(図
1C参照)とが順次接着積層される。且つ、前記下部充
填物質層14においては、図1(B)に示すように、矩
形状をなしてその表面には所定間隔を置いてマトリック
ス形状に複数個のホール15が穿孔形成されている。そ
れらホール15の形状は後述するソルダボール16の形
状に従い多様な形態に穿孔形成されるが、楕円形が最も
好ましい。
【0010】叉、図1(C)に示しように半導体チップ
18は、BGA(Ball Grid Array)パッケージと同様
に、その上面に複数個のソルダボール16が付着形成さ
れ、それらソルダボール16は、前記各ホール15の該
当のホール内に夫々挿合されるように形成される。
【0011】更に、図1(A)に示すように、前記印刷
回路基板13の上面に下部充填物質層14が積層され、
その上面に前記半導体チップ18が積層されるが、この
場合、図2に示すように、前記下部充填物質層14上面
に半導体チップ18が緊密に挿合して積層される。該下
部充填物質層14の高さdはソルダボール16の高さ
d’よりも低く形成することが好ましい。
【0012】そして、それら下部充填物質総14及び半
導体チップ18の接着連結構造形成過程においては、図
3(A)に示すように、印刷回路基板13上にソルダボ
ールの形成された半導体チップ18を位置させ熱と圧力
とを加えてボンディング工程を行う。すると、前記ソル
ダボール16は所定高さGだけ圧着され、その後下部充
填物質層14が圧着手段(図示せず)により圧着され
る。その結果、前記下部充填物質層14は、横手方向及
び縦方向に圧着されて図3(A)の幅W1から図3
(B)の幅W2程度に増大される。このようにして完成
されたフリップチップパッケージは、図3(B)に示す
ように、下部充填領域19が下部充填物質層14(図3
Aを参照)を圧着して形成され、ソルダボール16には
なんの影響も与えないで半導体チップ18と印刷回路基
板13とは永久的に接着力が維持され、製品の信頼性が
向上される。
【0013】且つ、このような本発明に係る半導体素子
の基板上接着連結構造は、一度の工程によりソルダボー
ルを下部充填物質層14に圧着して半導体チップを基板
上に連結するので、原価が減少される。
【0014】
【発明の効果】以上説明したように、本発明に係る半導
体素子の基板上接着連結構造においては、半導体チップ
上のソルだボール叉は金属バンプを基板にボンディング
すると同時に下部充填物質を行うようになっているた
め、製造工程が簡単になり生産性が向上して原価が減少
されるという効果がある。叉、基板上に下部充填物質を
塗布し半導体チップを圧着するようになるため半導体チ
ップと印刷回路基板間の界面接着力が増大され、半導体
チップと印刷回路基板間のボイド(void)が除去さ
れ半導体パッケージの信頼性が向上されるという効果が
ある。
【図面の簡単な説明】
【図1】(A)(B)(C):本発明に係る半導体素子
の基板上接着連結構造を示した斜視図で、(A)は本発
明に係る半導体素子の基板上接着連結構造を示した一部
斜視図、(B)は本発明に係る下部充填物質層を示した
斜視図、(C)は本発明に係る半導体チップを示した斜
視図である。
【図2】図1のB−B線縦断面図である。
【図3】(A)(B):本発明に係る半導体素子の基板
上接着構造形成過程表示図で、(A)は下部充填物質層
の圧縮過程を示した断面図、(B)は完成されたフリッ
プチップパッケージを示した断面図である。
【図4】(A)(B):従来フリップチップパッケージ
の基板上連結構造を示した概略斜視図で、(A)は概略
斜視図、(B)は(A)のA−A線断面図である。
【符号の説明】
1、18:半導体チップ 2、16:ソルダボール 3、13:印刷回路基板 4、19:下部充填領域 7:ノズル 14:下部充填物質層 15:ホール

Claims (3)

    【特許請求の範囲】
  1. 【請求項1】基板に半導体素子を接着する連結構造であ
    って、 複数個のソルダボールの付着された半導体チップと、 該半導体チップと基板上面間に接着され、複数個のホー
    ルが穿孔形成された下部充填物質層と、から形成された
    半導体素子の基板上接着連結構造。
  2. 【請求項2】前記下部充填物質層は、その高さが前記ソ
    ルダボールよりも低く形成される請求項1記載の半導体
    素子の基板上接着連結構造。
  3. 【請求項3】前記下部充填物質層に夫々穿孔形成される
    各ホールは、前記各ソルダボールが夫々挿合されるよう
    に穿孔形成される請求項1記載の半導体素子の基板上接
    着連結構造。
JP8003453A 1995-09-22 1996-01-12 半導体素子の基板上接着連結構造 Pending JPH09172038A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR95P31431 1995-09-22
KR1019950031431A KR0157899B1 (ko) 1995-09-22 1995-09-22 기판에 반도체 장치를 부착시키기 위한 연결구조

Publications (1)

Publication Number Publication Date
JPH09172038A true JPH09172038A (ja) 1997-06-30

Family

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JP8003453A Pending JPH09172038A (ja) 1995-09-22 1996-01-12 半導体素子の基板上接着連結構造

Country Status (4)

Country Link
US (2) US5703406A (ja)
JP (1) JPH09172038A (ja)
KR (1) KR0157899B1 (ja)
CN (1) CN1072840C (ja)

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US6075710A (en) * 1998-02-11 2000-06-13 Express Packaging Systems, Inc. Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips
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JP3975569B2 (ja) * 1998-09-01 2007-09-12 ソニー株式会社 実装基板及びその製造方法
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CN1720490B (zh) * 2002-11-15 2010-12-08 应用材料有限公司 用于控制具有多变量输入参数的制造工艺的方法和系统
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CN1072840C (zh) 2001-10-10
KR0157899B1 (ko) 1998-12-01
CN1149764A (zh) 1997-05-14
US5703406A (en) 1997-12-30
US5883438A (en) 1999-03-16
KR970018433A (ko) 1997-04-30

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