JP2002526917A - トランジスタの製造方法 - Google Patents

トランジスタの製造方法

Info

Publication number
JP2002526917A
JP2002526917A JP2000572912A JP2000572912A JP2002526917A JP 2002526917 A JP2002526917 A JP 2002526917A JP 2000572912 A JP2000572912 A JP 2000572912A JP 2000572912 A JP2000572912 A JP 2000572912A JP 2002526917 A JP2002526917 A JP 2002526917A
Authority
JP
Japan
Prior art keywords
doped
region
semiconductor substrate
trench
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000572912A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002526917A5 (https=
Inventor
ハルトムート グリューツェディエク、
ヨアヒム シェーラー、
Original Assignee
グリューツェディエク、 ウルスラ
シェーラー、 ユッタ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by グリューツェディエク、 ウルスラ, シェーラー、 ユッタ filed Critical グリューツェディエク、 ウルスラ
Publication of JP2002526917A publication Critical patent/JP2002526917A/ja
Publication of JP2002526917A5 publication Critical patent/JP2002526917A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0116—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including integrated injection logic [I2L]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/645—Combinations of only lateral BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
JP2000572912A 1998-09-29 1999-08-13 トランジスタの製造方法 Pending JP2002526917A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19844531.8A DE19844531B4 (de) 1998-09-29 1998-09-29 Verfahren zur Herstellung von Transistoren
DE19844531.8 1998-09-29
PCT/EP1999/005942 WO2000019503A1 (de) 1998-09-29 1999-08-13 Verfahren zur herstellung von transistoren

Publications (2)

Publication Number Publication Date
JP2002526917A true JP2002526917A (ja) 2002-08-20
JP2002526917A5 JP2002526917A5 (https=) 2006-11-02

Family

ID=7882576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000572912A Pending JP2002526917A (ja) 1998-09-29 1999-08-13 トランジスタの製造方法

Country Status (7)

Country Link
US (1) US7271070B1 (https=)
EP (1) EP1129476A1 (https=)
JP (1) JP2002526917A (https=)
CN (1) CN1151544C (https=)
AU (2) AU5622099A (https=)
DE (1) DE19844531B4 (https=)
WO (2) WO2000019503A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2026056503A (ja) * 2024-09-19 2026-04-01 ディービー ハイテック カンパニー リミテッド 半導体装置およびその製造方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10057163A1 (de) * 2000-11-16 2002-05-23 Gruetzediek Ursula Verfahren zur Herstellung von Halbleiterbauelementen mit Schottky-Übergängen
JP3812421B2 (ja) * 2001-06-14 2006-08-23 住友電気工業株式会社 横型接合型電界効果トランジスタ
DE102004016992B4 (de) 2004-04-02 2009-02-05 Prema Semiconductor Gmbh Verfahren zur Herstellung eines Bipolar-Transistors
EP1670052B1 (de) 2004-12-08 2010-10-20 PREMA Semiconductor GmbH Verfahren zur Herstellung einer Halbleiteranordnung mit einer spannungsfesten PMOSFET-Halbleiterstruktur und einer NMOSFET-Halbleiterstruktur
US7550787B2 (en) * 2005-05-31 2009-06-23 International Business Machines Corporation Varied impurity profile region formation for varying breakdown voltage of devices
US20080128762A1 (en) * 2006-10-31 2008-06-05 Vora Madhukar B Junction isolated poly-silicon gate JFET

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5173887A (ja) * 1974-12-23 1976-06-26 Fujitsu Ltd Handotaisochinoseizohoho
JPS51113469A (en) * 1975-03-31 1976-10-06 Fujitsu Ltd Manufacturing method of semiconductor device
JPS55105378A (en) * 1979-02-07 1980-08-12 Toshiba Corp Negative resistance semiconductor element
JPS60107858A (ja) * 1983-11-17 1985-06-13 Toshiba Corp ダ−リントンフオトトランジスタ
JPS62145867A (ja) * 1985-12-20 1987-06-29 Matsushita Electric Ind Co Ltd イメ−ジセンサ
JPH027462A (ja) * 1988-01-21 1990-01-11 Exar Corp ＢｉＣＭＯＳ装置製造方法
JPH03174741A (ja) * 1989-09-29 1991-07-29 Toshiba Corp 電力用ｉｃおよびその製造方法
JPH0492466A (ja) * 1990-08-07 1992-03-25 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH05129429A (ja) * 1991-07-17 1993-05-25 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH06120437A (ja) * 1992-09-30 1994-04-28 Mitsumi Electric Co Ltd バイポーラｉｃの構造及び製造方法
JPH1050994A (ja) * 1996-08-05 1998-02-20 Sharp Corp 半導体装置の製造方法

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US3925120A (en) * 1969-10-27 1975-12-09 Hitachi Ltd A method for manufacturing a semiconductor device having a buried epitaxial layer
US3981072A (en) * 1973-05-25 1976-09-21 Trw Inc. Bipolar transistor construction method
US4086610A (en) * 1974-06-28 1978-04-25 Motorola, Inc. High reliability epi-base radiation hardened power transistor
GB2023340B (en) * 1978-06-01 1982-09-02 Mitsubishi Electric Corp Integrated circuits
DE2922250A1 (de) 1979-05-31 1980-12-11 Siemens Ag Lichtsteuerbarer transistor
GB2056768B (en) * 1979-07-16 1983-07-27 Matsushita Electric Industrial Co Ltd Semiconductor integrated circuits
JPS5824018B2 (ja) * 1979-12-21 1983-05-18 富士通株式会社 バイポ−ラｉｃの製造方法
JPS5724548A (en) 1980-07-22 1982-02-09 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPH0824131B2 (ja) * 1985-10-07 1996-03-06 株式会社日立製作所 電界効果トランジスタ
JP2505767B2 (ja) 1986-09-18 1996-06-12 キヤノン株式会社 光電変換装置の製造方法
NL8701251A (nl) 1987-05-26 1988-12-16 Philips Nv Halfgeleiderinrichting en werkwijze ter vervaardiging daarvan.
US5292671A (en) * 1987-10-08 1994-03-08 Matsushita Electric Industrial, Co., Ltd. Method of manufacture for semiconductor device by forming deep and shallow regions
EP0339386B1 (de) 1988-04-29 1994-07-13 Siemens Aktiengesellschaft Als Fotodetektor verwendbare Bipolartransistorstruktur
JPH0494545A (ja) * 1990-08-10 1992-03-26 Fujitsu Ltd バイポーラトランジスタ
JPH05226351A (ja) * 1992-02-17 1993-09-03 Sharp Corp 半導体装置の製造方法
DE69530881D1 (de) * 1994-03-18 2003-07-03 Hitachi Ltd Halbleiteranordnung mit einem lateralen Bipolartransistor
US5428233A (en) * 1994-04-04 1995-06-27 Motorola Inc. Voltage controlled resistive device
US5444004A (en) * 1994-04-13 1995-08-22 Winbond Electronics Corporation CMOS process compatible self-alignment lateral bipolar junction transistor
KR0148296B1 (ko) * 1994-07-28 1998-12-01 문정환 반도체 소자의 격리방법
JPH08195399A (ja) * 1994-09-22 1996-07-30 Texas Instr Inc <Ti> 埋込み層を必要としない絶縁された垂直ｐｎｐトランジスタ
US5702959A (en) * 1995-05-31 1997-12-30 Texas Instruments Incorporated Method for making an isolated vertical transistor
JPH0927551A (ja) * 1995-07-12 1997-01-28 Olympus Optical Co Ltd 半導体装置の製造方法
US5858828A (en) 1997-02-18 1999-01-12 Symbios, Inc. Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5173887A (ja) * 1974-12-23 1976-06-26 Fujitsu Ltd Handotaisochinoseizohoho
JPS51113469A (en) * 1975-03-31 1976-10-06 Fujitsu Ltd Manufacturing method of semiconductor device
JPS55105378A (en) * 1979-02-07 1980-08-12 Toshiba Corp Negative resistance semiconductor element
JPS60107858A (ja) * 1983-11-17 1985-06-13 Toshiba Corp ダ−リントンフオトトランジスタ
JPS62145867A (ja) * 1985-12-20 1987-06-29 Matsushita Electric Ind Co Ltd イメ−ジセンサ
JPH027462A (ja) * 1988-01-21 1990-01-11 Exar Corp ＢｉＣＭＯＳ装置製造方法
JPH03174741A (ja) * 1989-09-29 1991-07-29 Toshiba Corp 電力用ｉｃおよびその製造方法
JPH0492466A (ja) * 1990-08-07 1992-03-25 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH05129429A (ja) * 1991-07-17 1993-05-25 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH06120437A (ja) * 1992-09-30 1994-04-28 Mitsumi Electric Co Ltd バイポーラｉｃの構造及び製造方法
JPH1050994A (ja) * 1996-08-05 1998-02-20 Sharp Corp 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2026056503A (ja) * 2024-09-19 2026-04-01 ディービー ハイテック カンパニー リミテッド 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US7271070B1 (en) 2007-09-18
DE19844531B4 (de) 2017-12-14
CN1151544C (zh) 2004-05-26
AU5622099A (en) 2000-04-17
WO2000019535B1 (de) 2000-05-11
CN1324495A (zh) 2001-11-28
WO2000019535A1 (de) 2000-04-06
EP1129476A1 (de) 2001-09-05
DE19844531A1 (de) 2000-04-06
AU6330399A (en) 2000-04-17
WO2000019503A1 (de) 2000-04-06

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