JP2002524857A5 - - Google Patents

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Publication number
JP2002524857A5
JP2002524857A5 JP2000568124A JP2000568124A JP2002524857A5 JP 2002524857 A5 JP2002524857 A5 JP 2002524857A5 JP 2000568124 A JP2000568124 A JP 2000568124A JP 2000568124 A JP2000568124 A JP 2000568124A JP 2002524857 A5 JP2002524857 A5 JP 2002524857A5
Authority
JP
Japan
Prior art keywords
conductive
plug
dielectric layer
width
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000568124A
Other languages
English (en)
Japanese (ja)
Other versions
JP3898891B2 (ja
JP2002524857A (ja
Filing date
Publication date
Priority claimed from US09/141,217 external-priority patent/US6400018B2/en
Application filed filed Critical
Publication of JP2002524857A publication Critical patent/JP2002524857A/ja
Publication of JP2002524857A5 publication Critical patent/JP2002524857A5/ja
Application granted granted Critical
Publication of JP3898891B2 publication Critical patent/JP3898891B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000568124A 1998-08-27 1999-01-15 バイアプラグアダプター Expired - Fee Related JP3898891B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/141,217 US6400018B2 (en) 1998-08-27 1998-08-27 Via plug adapter
US09/141,217 1998-08-27
PCT/US1999/000179 WO2000013232A1 (en) 1998-08-27 1999-01-15 Through hole bump contact

Publications (3)

Publication Number Publication Date
JP2002524857A JP2002524857A (ja) 2002-08-06
JP2002524857A5 true JP2002524857A5 (enExample) 2005-09-15
JP3898891B2 JP3898891B2 (ja) 2007-03-28

Family

ID=22494705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000568124A Expired - Fee Related JP3898891B2 (ja) 1998-08-27 1999-01-15 バイアプラグアダプター

Country Status (10)

Country Link
US (2) US6400018B2 (enExample)
EP (1) EP1118119A1 (enExample)
JP (1) JP3898891B2 (enExample)
KR (1) KR100367126B1 (enExample)
CN (1) CN1192429C (enExample)
AU (1) AU2451399A (enExample)
CA (1) CA2338550A1 (enExample)
IL (1) IL141051A0 (enExample)
TW (1) TW463348B (enExample)
WO (1) WO2000013232A1 (enExample)

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US6744640B2 (en) 2002-04-10 2004-06-01 Gore Enterprise Holdings, Inc. Board-level EMI shield with enhanced thermal dissipation
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US20040099716A1 (en) * 2002-11-27 2004-05-27 Motorola Inc. Solder joint reliability by changing solder pad surface from flat to convex shape
US7060624B2 (en) * 2003-08-13 2006-06-13 International Business Machines Corporation Deep filled vias
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
JP2005175128A (ja) * 2003-12-10 2005-06-30 Fujitsu Ltd 半導体装置及びその製造方法
US7446399B1 (en) 2004-08-04 2008-11-04 Altera Corporation Pad structures to improve board-level reliability of solder-on-pad BGA structures
US7267861B2 (en) * 2005-05-31 2007-09-11 Texas Instruments Incorporated Solder joints for copper metallization having reduced interfacial voids
TWI273667B (en) * 2005-08-30 2007-02-11 Via Tech Inc Chip package and bump connecting structure thereof
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US7544304B2 (en) 2006-07-11 2009-06-09 Electro Scientific Industries, Inc. Process and system for quality management and analysis of via drilling
JP5010948B2 (ja) * 2007-03-06 2012-08-29 オリンパス株式会社 半導体装置
US7886437B2 (en) * 2007-05-25 2011-02-15 Electro Scientific Industries, Inc. Process for forming an isolated electrically conductive contact through a metal package
US7892441B2 (en) * 2007-06-01 2011-02-22 General Dynamics Advanced Information Systems, Inc. Method and apparatus to change solder pad size using a differential pad plating
JP5501562B2 (ja) * 2007-12-13 2014-05-21 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
WO2009122912A1 (ja) * 2008-03-31 2009-10-08 三洋電機株式会社 はんだ構造体、はんだ構造体の形成方法、はんだ構造体を含む半導体モジュール、および携帯機器
US7943862B2 (en) * 2008-08-20 2011-05-17 Electro Scientific Industries, Inc. Method and apparatus for optically transparent via filling
TWI468093B (zh) * 2008-10-31 2015-01-01 Princo Corp 多層基板之導孔結構及其製造方法
TWI380423B (en) * 2008-12-29 2012-12-21 Advanced Semiconductor Eng Substrate structure and manufacturing method thereof
US8536458B1 (en) 2009-03-30 2013-09-17 Amkor Technology, Inc. Fine pitch copper pillar package and method
JP5195821B2 (ja) * 2010-06-03 2013-05-15 株式会社村田製作所 電子デバイスの製造方法
US8492893B1 (en) * 2011-03-16 2013-07-23 Amkor Technology, Inc. Semiconductor device capable of preventing dielectric layer from cracking
TWI449271B (zh) * 2011-11-16 2014-08-11 東琳精密股份有限公司 具有連接介面的電子裝置、其電路基板以及其製造方法
JP5971000B2 (ja) * 2012-07-20 2016-08-17 富士通株式会社 配線基板、配線基板の製造方法、電子機器及び電子機器の製造方法
CN107170689B (zh) * 2013-06-11 2019-12-31 唐山国芯晶源电子有限公司 芯片封装基板
US9231357B1 (en) * 2013-09-30 2016-01-05 Emc Corporation Mid-plane assembly
US9935081B2 (en) * 2014-08-20 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid interconnect for chip stacking
CN105636365B (zh) * 2014-10-27 2018-03-13 健鼎（无锡）电子有限公司 转接板的制作方法
US10359565B2 (en) 2017-02-07 2019-07-23 Nokia Of America Corporation Optoelectronic circuit having one or more double-sided substrates
US10068851B1 (en) * 2017-05-30 2018-09-04 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
EP3966897A4 (en) 2019-05-06 2023-11-01 3M Innovative Properties Company PATTERNED ARTICLE INCLUDING ELECTRICALLY CONDUCTIVE ELEMENTS
US11605576B2 (en) * 2019-06-25 2023-03-14 Semiconductor Components Industries, Llc Via for semiconductor devices and related methods
CN114864798A (zh) * 2021-01-20 2022-08-05 方略电子股份有限公司 衬底结构与电子装置
TWI742991B (zh) * 2021-01-20 2021-10-11 啟耀光電股份有限公司 基板結構與電子裝置
CN113038703B (zh) * 2021-03-17 2022-08-05 京东方科技集团股份有限公司 一种柔性电路板及其制造方法及电子设备
KR20220158177A (ko) * 2021-05-21 2022-11-30 삼성전자주식회사 반도체 패키지

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JPH08148603A (ja) 1994-11-22 1996-06-07 Nec Kyushu Ltd ボールグリッドアレイ型半導体装置およびその製造方法
JP2763020B2 (ja) 1995-04-27 1998-06-11 日本電気株式会社 半導体パッケージ及び半導体装置
JP3015712B2 (ja) 1995-06-30 2000-03-06 日東電工株式会社 フィルムキャリアおよびそれを用いてなる半導体装置
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JP3238074B2 (ja) 1996-07-25 2001-12-10 日立電線株式会社 半導体装置用テープキャリア
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US5973393A (en) * 1996-12-20 1999-10-26 Lsi Logic Corporation Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits
US6114187A (en) * 1997-01-11 2000-09-05 Microfab Technologies, Inc. Method for preparing a chip scale package and product produced by the method
US6114763A (en) * 1997-05-30 2000-09-05 Tessera, Inc. Semiconductor package with translator for connection to an external substrate
US5977632A (en) * 1998-02-02 1999-11-02 Motorola, Inc. Flip chip bump structure and method of making
US5943597A (en) * 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
US6400018B2 (en) * 1998-08-27 2002-06-04 3M Innovative Properties Company Via plug adapter

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