JP2002093949A5 - - Google Patents

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Publication number
JP2002093949A5
JP2002093949A5 JP2001218921A JP2001218921A JP2002093949A5 JP 2002093949 A5 JP2002093949 A5 JP 2002093949A5 JP 2001218921 A JP2001218921 A JP 2001218921A JP 2001218921 A JP2001218921 A JP 2001218921A JP 2002093949 A5 JP2002093949 A5 JP 2002093949A5
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit package
conductive layer
dielectric layer
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001218921A
Other languages
English (en)
Japanese (ja)
Other versions
JP4352365B2 (ja
JP2002093949A (ja
Filing date
Publication date
Priority claimed from US09/620,939 external-priority patent/US6465882B1/en
Application filed filed Critical
Publication of JP2002093949A publication Critical patent/JP2002093949A/ja
Publication of JP2002093949A5 publication Critical patent/JP2002093949A5/ja
Application granted granted Critical
Publication of JP4352365B2 publication Critical patent/JP4352365B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

JP2001218921A 2000-07-21 2001-07-19 集積回路パッケージの製造方法および集積回路パッケージ Expired - Lifetime JP4352365B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/620,939 US6465882B1 (en) 2000-07-21 2000-07-21 Integrated circuit package having partially exposed conductive layer
US09/620939 2000-07-21

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2008045768A Division JP5135493B2 (ja) 2000-07-21 2008-02-27 集積回路パッケージ

Publications (3)

Publication Number Publication Date
JP2002093949A JP2002093949A (ja) 2002-03-29
JP2002093949A5 true JP2002093949A5 (enExample) 2004-09-09
JP4352365B2 JP4352365B2 (ja) 2009-10-28

Family

ID=24488025

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2001218921A Expired - Lifetime JP4352365B2 (ja) 2000-07-21 2001-07-19 集積回路パッケージの製造方法および集積回路パッケージ
JP2008045768A Expired - Lifetime JP5135493B2 (ja) 2000-07-21 2008-02-27 集積回路パッケージ

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2008045768A Expired - Lifetime JP5135493B2 (ja) 2000-07-21 2008-02-27 集積回路パッケージ

Country Status (5)

Country Link
US (1) US6465882B1 (enExample)
JP (2) JP4352365B2 (enExample)
KR (1) KR100678878B1 (enExample)
GB (1) GB2370413B (enExample)
TW (1) TW512503B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6790760B1 (en) * 2000-07-21 2004-09-14 Agere Systems Inc. Method of manufacturing an integrated circuit package
DE10109542B4 (de) * 2001-02-28 2004-02-05 Siemens Ag Anordung zur Verbindung eines auf einer Leiterplatte angebrachten Bauelementes mit einer flexiblen Schichtanordnung
JP2005500638A (ja) * 2001-08-10 2005-01-06 シーゲイト テクノロジー エルエルシー 集積相互接続とその製造方法
DE10233607B4 (de) * 2002-07-24 2005-09-29 Siemens Ag Anordnung mit einem Halbleiterchip und einem mit einer Durchkontaktierung versehenen Träger sowie einem ein Anschlusspad des Halbleiterchips mit der Durchkontaktierung verbindenden Draht und Verfahren zum Herstellen einer solchen Anordnung
US7423340B2 (en) * 2003-01-21 2008-09-09 Siliconware Precision Industries Co., Ltd. Semiconductor package free of substrate and fabrication method thereof
TWI241000B (en) * 2003-01-21 2005-10-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabricating method thereof
US20040183167A1 (en) * 2003-03-21 2004-09-23 Texas Instruments Incorporated Recessed-bond semiconductor package substrate
US6956286B2 (en) * 2003-08-05 2005-10-18 International Business Machines Corporation Integrated circuit package with overlapping bond fingers
US7166905B1 (en) 2004-10-05 2007-01-23 Integrated Device Technology, Inc. Stacked paddle micro leadframe package
TWI286917B (en) * 2005-01-14 2007-09-11 Au Optronics Corp Thermal bonding structure and manufacture process of flexible printed circuit (FPC)
TW200703606A (en) * 2005-07-15 2007-01-16 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
US8447700B2 (en) 2005-10-11 2013-05-21 Amazon Technologies, Inc. Transaction authorization service
JPWO2010090075A1 (ja) * 2009-02-05 2012-08-09 アルプス電気株式会社 磁気検出装置
CN103000539B (zh) * 2012-11-16 2016-05-18 日月光半导体制造股份有限公司 半导体封装构造及其制造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4320438A (en) 1980-05-15 1982-03-16 Cts Corporation Multi-layer ceramic package
JPH01258447A (ja) * 1988-04-08 1989-10-16 Nec Corp 混成集積回路の積層厚膜基板
JPH07112039B2 (ja) * 1991-03-14 1995-11-29 日立電線株式会社 多ピン多層配線リードフレーム
US5196725A (en) * 1990-06-11 1993-03-23 Hitachi Cable Limited High pin count and multi-layer wiring lead frame
US5220195A (en) * 1991-12-19 1993-06-15 Motorola, Inc. Semiconductor device having a multilayer leadframe with full power and ground planes
JP3325351B2 (ja) * 1993-08-18 2002-09-17 株式会社東芝 半導体装置
US5490324A (en) 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
JP2931741B2 (ja) 1993-09-24 1999-08-09 株式会社東芝 半導体装置
JPH07288385A (ja) 1994-04-19 1995-10-31 Hitachi Chem Co Ltd 多層配線板及びその製造法
US5741729A (en) * 1994-07-11 1998-04-21 Sun Microsystems, Inc. Ball grid array package for an integrated circuit
US5622588A (en) 1995-02-02 1997-04-22 Hestia Technologies, Inc. Methods of making multi-tier laminate substrates for electronic device packaging
JPH08288316A (ja) * 1995-04-14 1996-11-01 Citizen Watch Co Ltd 半導体装置
US5689091A (en) 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US6054758A (en) 1996-12-18 2000-04-25 Texas Instruments Incorporated Differential pair geometry for integrated circuit chip packages
JPH1174651A (ja) 1997-03-13 1999-03-16 Ibiden Co Ltd プリント配線板及びその製造方法
JPH11204688A (ja) * 1997-11-11 1999-07-30 Sony Corp 半導体パッケージおよびその製造方法
US6064113A (en) * 1998-01-13 2000-05-16 Lsi Logic Corporation Semiconductor device package including a substrate having bonding fingers within an electrically conductive ring surrounding a die area and a combined power and ground plane to stabilize signal path impedances
JPH11266068A (ja) * 1998-01-14 1999-09-28 Canon Inc 配線基板及び配線基板の製造方法
JPH11354566A (ja) * 1998-06-08 1999-12-24 Hitachi Ltd 半導体装置およびその製造方法

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