JP2002299591A5 - - Google Patents

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Publication number
JP2002299591A5
JP2002299591A5 JP2001101514A JP2001101514A JP2002299591A5 JP 2002299591 A5 JP2002299591 A5 JP 2002299591A5 JP 2001101514 A JP2001101514 A JP 2001101514A JP 2001101514 A JP2001101514 A JP 2001101514A JP 2002299591 A5 JP2002299591 A5 JP 2002299591A5
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JP
Japan
Prior art keywords
element formation
formation region
semiconductor
disposed
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001101514A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002299591A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2001101514A priority Critical patent/JP2002299591A/ja
Priority claimed from JP2001101514A external-priority patent/JP2002299591A/ja
Priority to TW091105637A priority patent/TW533554B/zh
Priority to KR1020020016777A priority patent/KR100579780B1/ko
Priority to EP02252283A priority patent/EP1246248A3/en
Priority to CNB021180431A priority patent/CN1260804C/zh
Priority to US10/108,648 priority patent/US6593627B2/en
Publication of JP2002299591A publication Critical patent/JP2002299591A/ja
Publication of JP2002299591A5 publication Critical patent/JP2002299591A5/ja
Pending legal-status Critical Current

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JP2001101514A 2001-03-30 2001-03-30 半導体装置 Pending JP2002299591A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2001101514A JP2002299591A (ja) 2001-03-30 2001-03-30 半導体装置
TW091105637A TW533554B (en) 2001-03-30 2002-03-22 Semiconductor wafer and its manufacturing method, semiconductor device and its manufacturing method
KR1020020016777A KR100579780B1 (ko) 2001-03-30 2002-03-27 반도제장치 및 그 제조방법
EP02252283A EP1246248A3 (en) 2001-03-30 2002-03-28 SOI semiconductor wafer and semiconductor device formed therein
CNB021180431A CN1260804C (zh) 2001-03-30 2002-03-29 半导体晶片及其制造方法以及半导体器件及其制造方法
US10/108,648 US6593627B2 (en) 2001-03-30 2002-03-29 SOI semiconductor wafer having different thickness active layers and semiconductor device formed therein

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001101514A JP2002299591A (ja) 2001-03-30 2001-03-30 半導体装置

Publications (2)

Publication Number Publication Date
JP2002299591A JP2002299591A (ja) 2002-10-11
JP2002299591A5 true JP2002299591A5 (enExample) 2005-07-14

Family

ID=18954811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001101514A Pending JP2002299591A (ja) 2001-03-30 2001-03-30 半導体装置

Country Status (6)

Country Link
US (1) US6593627B2 (enExample)
EP (1) EP1246248A3 (enExample)
JP (1) JP2002299591A (enExample)
KR (1) KR100579780B1 (enExample)
CN (1) CN1260804C (enExample)
TW (1) TW533554B (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW536802B (en) * 2002-04-22 2003-06-11 United Microelectronics Corp Structure and fabrication method of electrostatic discharge protection circuit
FR2847077B1 (fr) * 2002-11-12 2006-02-17 Soitec Silicon On Insulator Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation
US6815714B1 (en) 2003-02-20 2004-11-09 National Semiconductor Corporation Conductive structure in a semiconductor material
US6812486B1 (en) * 2003-02-20 2004-11-02 National Semiconductor Corporation Conductive structure and method of forming the structure
DE102004005506B4 (de) 2004-01-30 2009-11-19 Atmel Automotive Gmbh Verfahren zur Erzeugung von aktiven Halbleiterschichten verschiedener Dicke in einem SOI-Wafer
DE102004005951B4 (de) * 2004-02-02 2005-12-29 Atmel Germany Gmbh Verfahren zur Herstellung von vertikal isolierten Bauelementen auf SOI-Material unterschiedlicher Dicke
JP2006041422A (ja) 2004-07-30 2006-02-09 Seiko Epson Corp 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法
JP2006073627A (ja) * 2004-08-31 2006-03-16 Toshiba Corp 半導体集積装置
US7141457B2 (en) * 2004-11-18 2006-11-28 International Business Machines Corporation Method to form Si-containing SOI and underlying substrate with different orientations
JP2006156867A (ja) 2004-12-01 2006-06-15 Seiko Epson Corp 半導体基板の製造方法および半導体装置の製造方法
FR2881273B1 (fr) * 2005-01-21 2007-05-04 St Microelectronics Sa Procede de formation d'un substrat semi-conducteur de circuit integre
JP2006253181A (ja) 2005-03-08 2006-09-21 Seiko Epson Corp 半導体装置および半導体装置の製造方法
JP4293193B2 (ja) 2005-03-09 2009-07-08 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
JP2006278632A (ja) 2005-03-29 2006-10-12 Seiko Epson Corp 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法
JP4029885B2 (ja) 2005-03-29 2008-01-09 セイコーエプソン株式会社 半導体装置の製造方法
JP2007027231A (ja) 2005-07-13 2007-02-01 Seiko Epson Corp 半導体装置の製造方法及び、半導体装置
US7459367B2 (en) * 2005-07-27 2008-12-02 International Business Machines Corporation Method of forming a vertical P-N junction device
JP4940797B2 (ja) 2005-10-03 2012-05-30 セイコーエプソン株式会社 半導体装置の製造方法
JP5130621B2 (ja) * 2005-11-24 2013-01-30 ソニー株式会社 半導体基板の製造方法
JP2007165676A (ja) 2005-12-15 2007-06-28 Seiko Epson Corp 半導体基板の製造方法及び半導体装置
JP2007194315A (ja) 2006-01-18 2007-08-02 Seiko Epson Corp 半導体装置および半導体装置の製造方法
US7666721B2 (en) 2006-03-15 2010-02-23 International Business Machines Corporation SOI substrates and SOI devices, and methods for forming the same
US7285480B1 (en) * 2006-04-07 2007-10-23 International Business Machines Corporation Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof
US7812367B2 (en) * 2008-10-15 2010-10-12 Semiconductor Components Industries, Llc Two terminal low capacitance multi-channel ESD device
JP2010141244A (ja) * 2008-12-15 2010-06-24 Mitsumi Electric Co Ltd 半導体装置
CN102986011B (zh) * 2010-08-12 2016-05-11 富士电机株式会社 半导体器件的制造方法
KR20130017914A (ko) * 2011-08-12 2013-02-20 삼성전자주식회사 광전 집적회로 기판 및 그 제조방법
US10115587B2 (en) * 2012-02-23 2018-10-30 Fuji Electric Co., Ltd. Method of manufacturing semiconductor device
JP6034268B2 (ja) * 2013-09-13 2016-11-30 株式会社東芝 半導体装置
JP6173988B2 (ja) * 2014-08-28 2017-08-02 株式会社ジャパンディスプレイ 電極基板の製造方法、電極基板、表示装置および入力装置
EP3742476B1 (en) * 2019-05-20 2024-11-06 Infineon Technologies AG Method of implanting an implant species into a substrate at different depths
CN111554186B (zh) * 2020-04-29 2022-05-17 昆山国显光电有限公司 离型层结构和显示面板的制备方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5102809A (en) * 1990-10-11 1992-04-07 Texas Instruments Incorporated SOI BICMOS process
JPH0685177A (ja) * 1992-08-31 1994-03-25 Hitachi Ltd 半導体集積回路装置
JP3191835B2 (ja) * 1993-05-17 2001-07-23 住友電気工業株式会社 光電子集積回路
US5364800A (en) * 1993-06-24 1994-11-15 Texas Instruments Incorporated Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate
JP3139904B2 (ja) * 1993-12-28 2001-03-05 新日本製鐵株式会社 半導体基板の製造方法および製造装置
JP2806286B2 (ja) * 1995-02-07 1998-09-30 日本電気株式会社 半導体装置
US5828112A (en) * 1995-09-18 1998-10-27 Kabushiki Kaisha Toshiba Semiconductor device incorporating an output element having a current-detecting section
US5708287A (en) * 1995-11-29 1998-01-13 Kabushiki Kaisha Toshiba Power semiconductor device having an active layer
JPH11163125A (ja) * 1997-12-01 1999-06-18 Hitachi Ltd Ｓｏｉ基板及びｓｏｉ基板の製造方法
JP2000164881A (ja) * 1998-11-30 2000-06-16 Seiko Instruments Inc 半導体装置とその製造方法

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