JP2002133857A5 - - Google Patents

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Publication number
JP2002133857A5
JP2002133857A5 JP2000333160A JP2000333160A JP2002133857A5 JP 2002133857 A5 JP2002133857 A5 JP 2002133857A5 JP 2000333160 A JP2000333160 A JP 2000333160A JP 2000333160 A JP2000333160 A JP 2000333160A JP 2002133857 A5 JP2002133857 A5 JP 2002133857A5
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JP
Japan
Prior art keywords
charge
data
memory cell
stored
storage means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000333160A
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English (en)
Japanese (ja)
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JP2002133857A (ja
JP4031904B2 (ja
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Publication date
Priority claimed from JP2000333160A external-priority patent/JP4031904B2/ja
Priority to JP2000333160A priority Critical patent/JP4031904B2/ja
Application filed filed Critical
Priority to US09/812,699 priority patent/US6487103B2/en
Priority to KR1020010019484A priority patent/KR100723894B1/ko
Publication of JP2002133857A publication Critical patent/JP2002133857A/ja
Priority to US10/272,997 priority patent/US6661697B2/en
Publication of JP2002133857A5 publication Critical patent/JP2002133857A5/ja
Priority to KR1020070041025A priority patent/KR100903045B1/ko
Publication of JP4031904B2 publication Critical patent/JP4031904B2/ja
Application granted granted Critical
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000333160A 2000-10-31 2000-10-31 データ読み出し回路とデータ読み出し方法及びデータ記憶装置 Expired - Fee Related JP4031904B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2000333160A JP4031904B2 (ja) 2000-10-31 2000-10-31 データ読み出し回路とデータ読み出し方法及びデータ記憶装置
US09/812,699 US6487103B2 (en) 2000-10-31 2001-03-21 Data read-out circuit, data read-out method, and data storage device
KR1020010019484A KR100723894B1 (ko) 2000-10-31 2001-04-12 데이터 판독 회로, 데이터 판독 방법 및 데이터 기억 장치
US10/272,997 US6661697B2 (en) 2000-10-31 2002-10-18 Data read-out circuit, data read-out method, and data storage device
KR1020070041025A KR100903045B1 (ko) 2000-10-31 2007-04-26 데이터 판독 회로, 데이터 판독 방법 및 데이터 기억 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000333160A JP4031904B2 (ja) 2000-10-31 2000-10-31 データ読み出し回路とデータ読み出し方法及びデータ記憶装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007225336A Division JP4550094B2 (ja) 2007-08-31 2007-08-31 データ記憶装置

Publications (3)

Publication Number Publication Date
JP2002133857A JP2002133857A (ja) 2002-05-10
JP2002133857A5 true JP2002133857A5 (enExample) 2004-12-02
JP4031904B2 JP4031904B2 (ja) 2008-01-09

Family

ID=18809278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000333160A Expired - Fee Related JP4031904B2 (ja) 2000-10-31 2000-10-31 データ読み出し回路とデータ読み出し方法及びデータ記憶装置

Country Status (3)

Country Link
US (2) US6487103B2 (enExample)
JP (1) JP4031904B2 (enExample)
KR (2) KR100723894B1 (enExample)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
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JP3794326B2 (ja) 2002-01-10 2006-07-05 富士通株式会社 負電圧生成回路及びこれを備えた強誘電体メモリ回路並びに集積回路装置
AU2003281556A1 (en) * 2002-07-23 2004-02-09 Matsushita Electric Industrial Co., Ltd. Ferroelectric gate device
CN100446118C (zh) * 2003-03-19 2008-12-24 富士通微电子株式会社 半导体存储装置
JP4185969B2 (ja) * 2003-04-10 2008-11-26 富士通マイクロエレクトロニクス株式会社 強誘電体メモリおよびそのデータ読み出し方法
US7193880B2 (en) * 2004-06-14 2007-03-20 Texas Instruments Incorporated Plateline voltage pulsing to reduce storage node disturbance in ferroelectric memory
JP2005129151A (ja) 2003-10-23 2005-05-19 Fujitsu Ltd 半導体記憶装置
US7009864B2 (en) * 2003-12-29 2006-03-07 Texas Instruments Incorporated Zero cancellation scheme to reduce plateline voltage in ferroelectric memory
JP4336212B2 (ja) 2004-01-26 2009-09-30 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
US7227769B2 (en) 2004-03-08 2007-06-05 Fujitsu Limited Semiconductor memory
JP4157528B2 (ja) 2004-03-08 2008-10-01 富士通株式会社 半導体メモリ
US7133304B2 (en) * 2004-03-22 2006-11-07 Texas Instruments Incorporated Method and apparatus to reduce storage node disturbance in ferroelectric memory
US6970371B1 (en) * 2004-05-17 2005-11-29 Texas Instruments Incorporated Reference generator system and methods for reading ferroelectric memory cells using reduced bitline voltages
JP4064951B2 (ja) 2004-07-28 2008-03-19 株式会社東芝 強誘電体半導体記憶装置
JP2006179048A (ja) * 2004-12-21 2006-07-06 Sanyo Electric Co Ltd 半導体装置
JP4647313B2 (ja) * 2005-01-06 2011-03-09 富士通セミコンダクター株式会社 半導体メモリ
JP4452631B2 (ja) 2005-01-21 2010-04-21 パトレネラ キャピタル リミテッド， エルエルシー メモリ
JP2006260742A (ja) 2005-02-15 2006-09-28 Sanyo Electric Co Ltd メモリ
JP4186119B2 (ja) 2005-07-27 2008-11-26 セイコーエプソン株式会社 強誘電体メモリ装置
US20070103961A1 (en) * 2005-11-07 2007-05-10 Honeywell International Inc. RAM cell with soft error protection using ferroelectric material
JP4305960B2 (ja) * 2005-12-28 2009-07-29 セイコーエプソン株式会社 強誘電体メモリ装置
JP4983062B2 (ja) * 2006-03-20 2012-07-25 富士通セミコンダクター株式会社 メモリ装置
JP4996177B2 (ja) * 2006-08-30 2012-08-08 富士通セミコンダクター株式会社 半導体記憶装置、およびデータ読み出し方法
JP4186169B2 (ja) 2006-09-01 2008-11-26 セイコーエプソン株式会社 強誘電体記憶装置および電子機器
JP4807192B2 (ja) * 2006-09-01 2011-11-02 セイコーエプソン株式会社 正電位変換回路、強誘電体記憶装置および電子機器
JP4807191B2 (ja) * 2006-09-01 2011-11-02 セイコーエプソン株式会社 強誘電体記憶装置および電子機器
JP4207077B2 (ja) 2006-10-02 2009-01-14 セイコーエプソン株式会社 強誘電体メモリ装置及びその駆動方法並びに電子機器
KR20080051076A (ko) 2006-12-04 2008-06-10 세이코 엡슨 가부시키가이샤 강유전체 기억 장치 및 전자 기기
US7561458B2 (en) * 2006-12-26 2009-07-14 Texas Instruments Incorporated Ferroelectric memory array for implementing a zero cancellation scheme to reduce plateline voltage in ferroelectric memory
US7916556B2 (en) 2007-01-09 2011-03-29 Sony Corporation Semiconductor memory device, sense amplifier circuit and memory cell reading method using a threshold correction circuitry
JP5024374B2 (ja) 2007-05-18 2012-09-12 富士通セミコンダクター株式会社 半導体メモリ
JP2008305469A (ja) 2007-06-06 2008-12-18 Toshiba Corp 半導体記憶装置
KR101139163B1 (ko) 2007-09-14 2012-04-26 후지쯔 세미컨덕터 가부시키가이샤 반도체 메모리
US7920404B2 (en) * 2007-12-31 2011-04-05 Texas Instruments Incorporated Ferroelectric memory devices with partitioned platelines
JP2009301658A (ja) 2008-06-13 2009-12-24 Seiko Epson Corp 強誘電体記憶装置、強誘電体記憶装置の駆動方法および電子機器
TWI480526B (zh) * 2009-12-24 2015-04-11 Seiko Epson Corp 紅外線檢測電路、感測器裝置及電子機器
JP5500051B2 (ja) 2010-11-22 2014-05-21 富士通セミコンダクター株式会社 強誘電体メモリ
JP6145972B2 (ja) * 2012-03-05 2017-06-14 富士通セミコンダクター株式会社 不揮発性ラッチ回路及びメモリ装置
JP6370649B2 (ja) * 2014-09-09 2018-08-08 エイブリック株式会社 データ読出し回路
US9638672B2 (en) * 2015-03-06 2017-05-02 Bongiovi Acoustics Llc System and method for acquiring acoustic information from a resonating body
US9552864B1 (en) * 2016-03-11 2017-01-24 Micron Technology, Inc. Offset compensation for ferroelectric memory cell sensing
US10192606B2 (en) * 2016-04-05 2019-01-29 Micron Technology, Inc. Charge extraction from ferroelectric memory cell using sense capacitors
US9858979B1 (en) * 2016-10-05 2018-01-02 Micron Technology, Inc. Reprogrammable non-volatile ferroelectric latch for use with a memory controller
US10388353B1 (en) * 2018-03-16 2019-08-20 Micron Technology, Inc. Canceling memory cell variations by isolating digit lines
US10803910B2 (en) 2018-07-25 2020-10-13 Fujitsu Semiconductor Limited Semiconductor storage device and read method thereof
US11043252B2 (en) 2018-07-25 2021-06-22 Fujitsu Semiconductor Memory Solution Limited Semiconductor storage device, read method thereof, and test method thereof
US10692557B1 (en) 2019-04-11 2020-06-23 Micron Technology, Inc. Reference voltage management

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3319637B2 (ja) * 1993-11-10 2002-09-03 松下電器産業株式会社 半導体記憶装置及びその制御方法
JPH09185890A (ja) * 1996-01-08 1997-07-15 Hitachi Ltd 強誘電体記憶装置
DE69736080T2 (de) * 1996-03-25 2006-10-19 Matsushita Electric Industrial Co., Ltd., Kadoma Ferroelekrische Speicheranordnung
JP3897388B2 (ja) * 1996-12-27 2007-03-22 シャープ株式会社 シリアルアクセス方式の半導体記憶装置
KR100256226B1 (ko) * 1997-06-26 2000-05-15 김영환 레퍼런스 전압 발생 장치
KR100275107B1 (ko) * 1997-12-30 2000-12-15 김영환 강유전체메모리장치및그구동방법

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