JP2000039985A5 - - Google Patents

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Publication number
JP2000039985A5
JP2000039985A5 JP1999119999A JP11999999A JP2000039985A5 JP 2000039985 A5 JP2000039985 A5 JP 2000039985A5 JP 1999119999 A JP1999119999 A JP 1999119999A JP 11999999 A JP11999999 A JP 11999999A JP 2000039985 A5 JP2000039985 A5 JP 2000039985A5
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JP
Japan
Prior art keywords
write
line
storage element
read
input
Prior art date
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Application number
JP1999119999A
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English (en)
Japanese (ja)
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JP2000039985A (ja
JP3954238B2 (ja
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Publication date
Priority claimed from US09/067,702 external-priority patent/US6188633B1/en
Application filed filed Critical
Publication of JP2000039985A publication Critical patent/JP2000039985A/ja
Publication of JP2000039985A5 publication Critical patent/JP2000039985A5/ja
Application granted granted Critical
Publication of JP3954238B2 publication Critical patent/JP3954238B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP11999999A 1998-04-28 1999-04-27 レジスタファイル Expired - Fee Related JP3954238B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US067702 1997-12-30
US09/067,702 US6188633B1 (en) 1998-04-28 1998-04-28 Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impedance state during write operations

Publications (3)

Publication Number Publication Date
JP2000039985A JP2000039985A (ja) 2000-02-08
JP2000039985A5 true JP2000039985A5 (enExample) 2005-07-21
JP3954238B2 JP3954238B2 (ja) 2007-08-08

Family

ID=22077796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11999999A Expired - Fee Related JP3954238B2 (ja) 1998-04-28 1999-04-27 レジスタファイル

Country Status (2)

Country Link
US (2) US6188633B1 (enExample)
JP (1) JP3954238B2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6188633B1 (en) * 1998-04-28 2001-02-13 Hewlett-Packard Company Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impedance state during write operations
US6564331B1 (en) * 1999-09-24 2003-05-13 Intel Corporation Low power register file
US20030154363A1 (en) * 2002-02-11 2003-08-14 Soltis Donald C. Stacked register aliasing in data hazard detection to reduce circuit
JP2004102799A (ja) * 2002-09-11 2004-04-02 Nec Electronics Corp レジスタファイル及びレジスタファイルの設計方法
US8108609B2 (en) * 2007-12-04 2012-01-31 International Business Machines Corporation Structure for implementing dynamic refresh protocols for DRAM based cache
US20090144504A1 (en) * 2007-12-04 2009-06-04 International Business Machines Corporation STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
US20090144507A1 (en) * 2007-12-04 2009-06-04 International Business Machines Corporation APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
US7882302B2 (en) * 2007-12-04 2011-02-01 International Business Machines Corporation Method and system for implementing prioritized refresh of DRAM based cache
US7962695B2 (en) * 2007-12-04 2011-06-14 International Business Machines Corporation Method and system for integrating SRAM and DRAM architecture in set associative cache
US8024513B2 (en) * 2007-12-04 2011-09-20 International Business Machines Corporation Method and system for implementing dynamic refresh protocols for DRAM based cache
CN101620524B (zh) * 2009-07-03 2011-08-10 中国人民解放军国防科学技术大学 支持矩阵整体读写操作的矩阵寄存器文件
US9207995B2 (en) 2010-11-03 2015-12-08 International Business Machines Corporation Mechanism to speed-up multithreaded execution by register file write port reallocation
US8432756B1 (en) * 2011-10-18 2013-04-30 Apple Inc. Collision prevention in a dual port memory
US9384825B2 (en) 2014-09-26 2016-07-05 Qualcomm Incorporated Multi-port memory circuits
CN108512783A (zh) * 2018-03-22 2018-09-07 新华三技术有限公司 一种状态信息获取方法及设备
US12498854B2 (en) * 2023-07-11 2025-12-16 Birad—Research & Development Company Ltd. Physically-driven generation of many-ported storage arrays

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2615088B2 (ja) * 1987-11-06 1997-05-28 株式会社日立製作所 半導体記憶装置
US5222240A (en) * 1990-02-14 1993-06-22 Intel Corporation Method and apparatus for delaying writing back the results of instructions to a processor
US5315178A (en) * 1993-08-27 1994-05-24 Hewlett-Packard Company IC which can be used as a programmable logic cell array or as a register file
US5481495A (en) * 1994-04-11 1996-01-02 International Business Machines Corporation Cells and read-circuits for high-performance register files
US5724299A (en) * 1996-04-30 1998-03-03 Sun Microsystems, Inc. Multiport register file memory using small voltage swing for write operation
JPH11184674A (ja) * 1997-12-24 1999-07-09 Fujitsu Ltd レジスタファイル
US6188633B1 (en) * 1998-04-28 2001-02-13 Hewlett-Packard Company Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impedance state during write operations

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