JP2002057212A - 半導体装置、及び半導体装置の製造方法 - Google Patents

半導体装置、及び半導体装置の製造方法

Info

Publication number
JP2002057212A
JP2002057212A JP2000241267A JP2000241267A JP2002057212A JP 2002057212 A JP2002057212 A JP 2002057212A JP 2000241267 A JP2000241267 A JP 2000241267A JP 2000241267 A JP2000241267 A JP 2000241267A JP 2002057212 A JP2002057212 A JP 2002057212A
Authority
JP
Japan
Prior art keywords
film
forming
adhesive layer
metal wiring
silicate glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000241267A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002057212A5 (https=
Inventor
Seiji Okura
誠司 大倉
Koji Oda
耕治 小田
Masato Sawada
真人 澤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000241267A priority Critical patent/JP2002057212A/ja
Priority to US09/802,951 priority patent/US6579787B2/en
Publication of JP2002057212A publication Critical patent/JP2002057212A/ja
Priority to US10/446,876 priority patent/US7012336B2/en
Priority to US11/291,994 priority patent/US20060081992A1/en
Publication of JP2002057212A5 publication Critical patent/JP2002057212A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/095—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by irradiating with electromagnetic or particle radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
JP2000241267A 2000-03-12 2000-08-09 半導体装置、及び半導体装置の製造方法 Pending JP2002057212A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000241267A JP2002057212A (ja) 2000-08-09 2000-08-09 半導体装置、及び半導体装置の製造方法
US09/802,951 US6579787B2 (en) 2000-08-09 2001-03-12 Semiconductor device with a fluorinated silicate glass film as an interlayer metal dielectric film, and manufacturing method thereof
US10/446,876 US7012336B2 (en) 2000-08-09 2003-05-29 Semiconductor device with a fluorinated silicate glass film as an interlayer metal dielectric film, and manufacturing method thereof
US11/291,994 US20060081992A1 (en) 2000-03-12 2005-12-02 Semiconductor device with a fluorinated silicate glass film as an interlayer metal dielectric film, and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000241267A JP2002057212A (ja) 2000-08-09 2000-08-09 半導体装置、及び半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2002057212A true JP2002057212A (ja) 2002-02-22
JP2002057212A5 JP2002057212A5 (https=) 2007-09-13

Family

ID=18732478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000241267A Pending JP2002057212A (ja) 2000-03-12 2000-08-09 半導体装置、及び半導体装置の製造方法

Country Status (2)

Country Link
US (3) US6579787B2 (https=)
JP (1) JP2002057212A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006163755A (ja) * 2004-12-07 2006-06-22 Oki Electric Ind Co Ltd サービス提供システムおよびポイント管理サーバおよびサービス提供方法
JP2007134424A (ja) * 2005-11-09 2007-05-31 Sony Corp 半導体装置の製造方法および半導体装置

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* Cited by examiner, † Cited by third party
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CN1278297C (zh) * 2001-11-09 2006-10-04 三洋电机株式会社 对光学元件的亮度数据具有初始化功能的显示器
JP2003186437A (ja) * 2001-12-18 2003-07-04 Sanyo Electric Co Ltd 表示装置
JP2003255899A (ja) * 2001-12-28 2003-09-10 Sanyo Electric Co Ltd 表示装置
JP3953330B2 (ja) 2002-01-25 2007-08-08 三洋電機株式会社 表示装置
JP3723507B2 (ja) * 2002-01-29 2005-12-07 三洋電機株式会社 駆動回路
JP2003295825A (ja) * 2002-02-04 2003-10-15 Sanyo Electric Co Ltd 表示装置
JP2003308030A (ja) 2002-02-18 2003-10-31 Sanyo Electric Co Ltd 表示装置
JP2003332058A (ja) * 2002-03-05 2003-11-21 Sanyo Electric Co Ltd エレクトロルミネッセンスパネルおよびその製造方法
JP2003258094A (ja) * 2002-03-05 2003-09-12 Sanyo Electric Co Ltd 配線構造、その製造方法、および表示装置
JP2003257645A (ja) * 2002-03-05 2003-09-12 Sanyo Electric Co Ltd 発光装置およびその製造方法
CN100517422C (zh) * 2002-03-07 2009-07-22 三洋电机株式会社 配线结构、其制造方法、以及光学设备
JP3671012B2 (ja) * 2002-03-07 2005-07-13 三洋電機株式会社 表示装置
JP3837344B2 (ja) * 2002-03-11 2006-10-25 三洋電機株式会社 光学素子およびその製造方法
JP3504940B2 (ja) * 2002-05-17 2004-03-08 沖電気工業株式会社 半導体装置の製造方法
KR100640981B1 (ko) * 2005-09-30 2006-11-02 동부일렉트로닉스 주식회사 이미지 센서의 제조방법
US7927990B2 (en) * 2007-06-29 2011-04-19 Sandisk Corporation Forming complimentary metal features using conformal insulator layer
US20090079072A1 (en) * 2007-09-21 2009-03-26 Casio Computer Co., Ltd. Semiconductor device having low dielectric insulating film and manufacturing method of the same
US8587124B2 (en) 2007-09-21 2013-11-19 Teramikros, Inc. Semiconductor device having low dielectric insulating film and manufacturing method of the same
TWI419268B (zh) * 2007-09-21 2013-12-11 兆裝微股份有限公司 半導體裝置及其製造方法
JP4666028B2 (ja) * 2008-03-31 2011-04-06 カシオ計算機株式会社 半導体装置
US8316862B2 (en) 2009-02-25 2012-11-27 University Of Maryland Devices, systems and methods for magnetic-assisted therapeutic agent delivery
CN105336674B (zh) * 2014-07-28 2018-03-30 中芯国际集成电路制造(上海)有限公司 互连结构及其形成方法

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US5753564A (en) * 1992-11-24 1998-05-19 Sumitomo Metal Industries, Ltd. Method for forming a thin film of a silicon oxide on a silicon substrate, by BCR plasma
JP3294413B2 (ja) * 1993-12-28 2002-06-24 富士通株式会社 半導体装置の製造方法及び製造装置
US6278174B1 (en) * 1994-04-28 2001-08-21 Texas Instruments Incorporated Integrated circuit insulator and structure using low dielectric insulator material including HSQ and fluorinated oxide
US6001728A (en) * 1996-03-15 1999-12-14 Applied Materials, Inc. Method and apparatus for improving film stability of halogen-doped silicon oxide films
US5827785A (en) * 1996-10-24 1998-10-27 Applied Materials, Inc. Method for improving film stability of fluorosilicate glass films
JP3409984B2 (ja) * 1996-11-14 2003-05-26 東京エレクトロン株式会社 半導体装置及び半導体装置の製造方法
KR100244967B1 (ko) 1996-12-26 2000-02-15 김영환 듀얼 게이트(dual-gate)의 반도체 장치 제조방법
US5958508A (en) * 1997-03-31 1999-09-28 Motorlola, Inc. Process for forming a semiconductor device
US5872065A (en) * 1997-04-02 1999-02-16 Applied Materials Inc. Method for depositing low K SI-O-F films using SIF4 /oxygen chemistry
US6121164A (en) * 1997-10-24 2000-09-19 Applied Materials, Inc. Method for forming low compressive stress fluorinated ozone/TEOS oxide film
US5953625A (en) * 1997-12-15 1999-09-14 Advanced Micro Devices, Inc. Air voids underneath metal lines to reduce parasitic capacitance
US5946601A (en) * 1997-12-31 1999-08-31 Intel Corporation Unique α-C:N:H/α-C:Nx film liner/barrier to prevent fluorine outdiffusion from α-FC chemical vapor deposition dielectric layers
JP4427108B2 (ja) * 1998-03-27 2010-03-03 株式会社東芝 半導体装置及びその製造方法
US6153509A (en) * 1998-07-01 2000-11-28 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
US6300672B1 (en) * 1998-07-22 2001-10-09 Siemens Aktiengesellschaft Silicon oxynitride cap for fluorinated silicate glass film in intermetal dielectric semiconductor fabrication
TW405223B (en) * 1998-07-28 2000-09-11 United Microelectronics Corp Method for avoiding the poisoning at the trench of the dual damascene structure and the dielectric hole
JP3877109B2 (ja) * 1998-12-02 2007-02-07 富士通株式会社 半導体装置およびその製造方法
JP2000216264A (ja) * 1999-01-22 2000-08-04 Mitsubishi Electric Corp Ｃｍｏｓ論理回路素子、半導体装置とその製造方法およびその製造方法において用いる半導体回路設計方法
US6239024B1 (en) * 1999-03-05 2001-05-29 United Microelectronics Corp. Method of filling gap with dielectrics
US6291331B1 (en) * 1999-10-04 2001-09-18 Taiwan Semiconductor Manufacturing Company Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue
US6153512A (en) * 1999-10-12 2000-11-28 Taiwan Semiconductor Manufacturing Company Process to improve adhesion of HSQ to underlying materials
US6117747A (en) * 1999-11-22 2000-09-12 Chartered Semiconductor Manufacturing Ltd. Integration of MOM capacitor into dual damascene process
US6376353B1 (en) * 2000-07-03 2002-04-23 Chartered Semiconductor Manufacturing Ltd. Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006163755A (ja) * 2004-12-07 2006-06-22 Oki Electric Ind Co Ltd サービス提供システムおよびポイント管理サーバおよびサービス提供方法
JP2007134424A (ja) * 2005-11-09 2007-05-31 Sony Corp 半導体装置の製造方法および半導体装置

Also Published As

Publication number Publication date
US20060081992A1 (en) 2006-04-20
US20020024145A1 (en) 2002-02-28
US6579787B2 (en) 2003-06-17
US20030211721A1 (en) 2003-11-13
US7012336B2 (en) 2006-03-14

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