JP2001222885A5 - - Google Patents

Download PDF

Info

Publication number
JP2001222885A5
JP2001222885A5 JP2000032636A JP2000032636A JP2001222885A5 JP 2001222885 A5 JP2001222885 A5 JP 2001222885A5 JP 2000032636 A JP2000032636 A JP 2000032636A JP 2000032636 A JP2000032636 A JP 2000032636A JP 2001222885 A5 JP2001222885 A5 JP 2001222885A5
Authority
JP
Japan
Prior art keywords
data
read
memory
buffer
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000032636A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001222885A (ja
JP3940539B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2000032636A priority Critical patent/JP3940539B2/ja
Priority claimed from JP2000032636A external-priority patent/JP3940539B2/ja
Priority to US09/775,544 priority patent/US6430103B2/en
Publication of JP2001222885A publication Critical patent/JP2001222885A/ja
Priority to US10/187,947 priority patent/US6714477B2/en
Publication of JP2001222885A5 publication Critical patent/JP2001222885A5/ja
Application granted granted Critical
Publication of JP3940539B2 publication Critical patent/JP3940539B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2000032636A 2000-02-03 2000-02-03 半導体集積回路 Expired - Fee Related JP3940539B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000032636A JP3940539B2 (ja) 2000-02-03 2000-02-03 半導体集積回路
US09/775,544 US6430103B2 (en) 2000-02-03 2001-02-05 Semiconductor integrated circuit device with memory banks and read buffer capable of storing data read out from one memory bank when data of another memory bank is outputting
US10/187,947 US6714477B2 (en) 2000-02-03 2002-07-03 Semiconductor integrated circuit device with memory blocks and a write buffer capable of storing write data from an external interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000032636A JP3940539B2 (ja) 2000-02-03 2000-02-03 半導体集積回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2006293469A Division JP4674865B2 (ja) 2006-10-30 2006-10-30 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2001222885A JP2001222885A (ja) 2001-08-17
JP2001222885A5 true JP2001222885A5 (enExample) 2005-02-10
JP3940539B2 JP3940539B2 (ja) 2007-07-04

Family

ID=18557214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000032636A Expired - Fee Related JP3940539B2 (ja) 2000-02-03 2000-02-03 半導体集積回路

Country Status (2)

Country Link
US (2) US6430103B2 (enExample)
JP (1) JP3940539B2 (enExample)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8050198B2 (en) * 1999-05-24 2011-11-01 Qualcomm Incorporated Method and system for scheduling data transmission in communication systems
JP3940539B2 (ja) * 2000-02-03 2007-07-04 株式会社日立製作所 半導体集積回路
US7120761B2 (en) 2000-12-20 2006-10-10 Fujitsu Limited Multi-port memory based on DRAM core
US6880056B2 (en) * 2002-03-28 2005-04-12 Hewlett-Packard Development, L.P. Memory array and method with simultaneous read/write capability
JP3816034B2 (ja) * 2002-07-16 2006-08-30 松下電器産業株式会社 メモリ混載半導体集積回路
US7515598B2 (en) * 2002-10-29 2009-04-07 Intel Corporation Configurable transmit and receive system interfaces for a network device
JP2004247566A (ja) * 2003-02-14 2004-09-02 Ricoh Co Ltd 半導体記憶装置
KR100546331B1 (ko) * 2003-06-03 2006-01-26 삼성전자주식회사 스택 뱅크들 마다 독립적으로 동작하는 멀티 포트 메모리장치
US6906964B2 (en) * 2003-06-27 2005-06-14 Hewlett-Packard Development Company, L.P. Multiple buffer memory interface
US20050007858A1 (en) * 2003-07-10 2005-01-13 Smith Kenneth K. Method and system for reducing power when writing information to MRAM
US20050097132A1 (en) * 2003-10-29 2005-05-05 Hewlett-Packard Development Company, L.P. Hierarchical storage system
JP4528087B2 (ja) * 2004-10-15 2010-08-18 富士通セミコンダクター株式会社 半導体メモリ
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US7590796B2 (en) 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US7580312B2 (en) 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US20070014168A1 (en) 2005-06-24 2007-01-18 Rajan Suresh N Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies
JP4226577B2 (ja) * 2005-08-22 2009-02-18 マイクロン テクノロジー インコーポレイテッド 構造化遅延スキューを用いたバッファリング技術
GB2444663B (en) 2005-09-02 2011-12-07 Metaram Inc Methods and apparatus of stacking drams
KR100721582B1 (ko) * 2005-09-29 2007-05-23 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자
DE102006045248A1 (de) * 2005-09-29 2007-04-19 Hynix Semiconductor Inc., Ichon Multiport-Speichervorrichtung mit serieller Eingabe-/Ausgabeschnittstelle
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
JP5061504B2 (ja) * 2006-05-25 2012-10-31 株式会社明電舎 デュアルポートメモリのアクセス権調停方式
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
KR100909805B1 (ko) * 2006-09-21 2009-07-29 주식회사 하이닉스반도체 멀티포트 메모리 장치
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US9710384B2 (en) * 2008-01-04 2017-07-18 Micron Technology, Inc. Microprocessor architecture having alternative memory access paths
US8972958B1 (en) 2012-10-23 2015-03-03 Convey Computer Multistage development workflow for generating a custom instruction set reconfigurable processor
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US7920433B2 (en) * 2008-01-09 2011-04-05 Qimonda Ag Method and apparatus for storage device with a logic unit and method for manufacturing same
US8032804B2 (en) * 2009-01-12 2011-10-04 Micron Technology, Inc. Systems and methods for monitoring a memory system
DE202010017690U1 (de) 2009-06-09 2012-05-29 Google, Inc. Programmierung von Dimm-Abschlusswiderstandswerten
JP5760556B2 (ja) * 2011-03-18 2015-08-12 富士通株式会社 ストレージ装置、制御装置およびストレージ装置制御方法
US10430190B2 (en) 2012-06-07 2019-10-01 Micron Technology, Inc. Systems and methods for selectively controlling multithreaded execution of executable code segments
US9842630B2 (en) 2013-10-16 2017-12-12 Rambus Inc. Memory component with adjustable core-to-interface data rate ratio
KR102373544B1 (ko) 2015-11-06 2022-03-11 삼성전자주식회사 요청 기반의 리프레쉬를 수행하는 메모리 장치, 메모리 시스템 및 메모리 장치의 동작방법
CN109416667A (zh) * 2015-11-12 2019-03-01 道达尔阶段公司 具有动态且可配置的响应的、使用两个存储器级的串行设备仿真器
US10108376B1 (en) * 2017-05-04 2018-10-23 Xilinx, Inc. Memory initialization
JP2020166346A (ja) * 2019-03-28 2020-10-08 ラピスセミコンダクタ株式会社 半導体記憶装置
EP4553665A1 (en) * 2023-09-27 2025-05-14 VeriSilicon Microelectronics (Shanghai) Co., Ltd. Cache, cache management method, and electronic device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2011518C (en) 1989-04-25 1993-04-20 Ronald N. Fortino Distributed cache dram chip and control method
JPH0711793B2 (ja) * 1989-07-13 1995-02-08 株式会社東芝 マイクロプロセッサ
CA2045791A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Branch performance in high speed processor
JP3400824B2 (ja) 1992-11-06 2003-04-28 三菱電機株式会社 半導体記憶装置
US6415353B1 (en) * 1998-10-01 2002-07-02 Monolithic System Technology, Inc. Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same
US6370073B2 (en) * 1998-10-01 2002-04-09 Monlithic System Technology, Inc. Single-port multi-bank memory system having read and write buffers and method of operating same
JP3940539B2 (ja) * 2000-02-03 2007-07-04 株式会社日立製作所 半導体集積回路

Similar Documents

Publication Publication Date Title
JP2001222885A5 (enExample)
KR100768729B1 (ko) 클록 동기형 다이나믹 메모리 및 클록 동기형 집적 회로
JP3490887B2 (ja) 同期型半導体記憶装置
KR100618068B1 (ko) 반도체 집적 회로 및 그 제어 방법
KR960001778B1 (ko) 이중포트메모리 및 그 데이터 전송방법
US20020154557A1 (en) Semiconductor memory apparatus
KR970012155A (ko) 로우 핀 카운트-와이드 메모리 장치와 시스템 및 방법
JPH11297071A5 (enExample)
KR100805528B1 (ko) 반도체 메모리 장치에서의 선택적 리프레시 방법 및 시스템
JP2006018984A (ja) 入出力回路
KR100790446B1 (ko) 스택뱅크 구조를 갖는 반도체 메모리 장치
JP4027577B2 (ja) 入出力ライン対等化回路及びこれを備えたメモリ装置
US6339560B1 (en) Semiconductor memory based on address transitions
KR100663771B1 (ko) 반도체 기억 장치
KR100543914B1 (ko) 리프레쉬 동작시 피크 전류를 줄일 수 있는 반도체 메모리장치
JP4127054B2 (ja) 半導体記憶装置
WO2004029980A2 (en) Refresh control circuit for ics with a memory array
KR20010102846A (ko) 동기형 반도체 기억 장치
JP4077140B2 (ja) 半導体記憶装置
JP2008192264A (ja) 半導体記憶装置
JP2001189081A (ja) 半導体メモリディバイス及びそのビットライン接続方法
JPH10255468A (ja) Ｄｒａｍのリフレッシュ装置
JP4119105B2 (ja) 半導体メモリ
JPH07147085A (ja) メモリ装置
KR100640786B1 (ko) 반도체 기억 소자의 워드 라인 인에이블 회로 및 방법