JP3940539B2 - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

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Publication number
JP3940539B2
JP3940539B2 JP2000032636A JP2000032636A JP3940539B2 JP 3940539 B2 JP3940539 B2 JP 3940539B2 JP 2000032636 A JP2000032636 A JP 2000032636A JP 2000032636 A JP2000032636 A JP 2000032636A JP 3940539 B2 JP3940539 B2 JP 3940539B2
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JP
Japan
Prior art keywords
read
data
write
memory
memory block
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Expired - Fee Related
Application number
JP2000032636A
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English (en)
Japanese (ja)
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JP2001222885A5 (enExample
JP2001222885A (ja
Inventor
道明 中山
秀樹 榊原
徹 小林
修一 宮岡
勇治 横山
英雄 澤本
正二 久米
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Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000032636A priority Critical patent/JP3940539B2/ja
Priority to US09/775,544 priority patent/US6430103B2/en
Publication of JP2001222885A publication Critical patent/JP2001222885A/ja
Priority to US10/187,947 priority patent/US6714477B2/en
Publication of JP2001222885A5 publication Critical patent/JP2001222885A5/ja
Application granted granted Critical
Publication of JP3940539B2 publication Critical patent/JP3940539B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2000032636A 2000-02-03 2000-02-03 半導体集積回路 Expired - Fee Related JP3940539B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000032636A JP3940539B2 (ja) 2000-02-03 2000-02-03 半導体集積回路
US09/775,544 US6430103B2 (en) 2000-02-03 2001-02-05 Semiconductor integrated circuit device with memory banks and read buffer capable of storing data read out from one memory bank when data of another memory bank is outputting
US10/187,947 US6714477B2 (en) 2000-02-03 2002-07-03 Semiconductor integrated circuit device with memory blocks and a write buffer capable of storing write data from an external interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000032636A JP3940539B2 (ja) 2000-02-03 2000-02-03 半導体集積回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2006293469A Division JP4674865B2 (ja) 2006-10-30 2006-10-30 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2001222885A JP2001222885A (ja) 2001-08-17
JP2001222885A5 JP2001222885A5 (enExample) 2005-02-10
JP3940539B2 true JP3940539B2 (ja) 2007-07-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000032636A Expired - Fee Related JP3940539B2 (ja) 2000-02-03 2000-02-03 半導体集積回路

Country Status (2)

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US (2) US6430103B2 (enExample)
JP (1) JP3940539B2 (enExample)

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US20050097132A1 (en) * 2003-10-29 2005-05-05 Hewlett-Packard Development Company, L.P. Hierarchical storage system
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US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
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US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
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US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
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Also Published As

Publication number Publication date
US6430103B2 (en) 2002-08-06
US6714477B2 (en) 2004-03-30
US20010012232A1 (en) 2001-08-09
US20020176308A1 (en) 2002-11-28
JP2001222885A (ja) 2001-08-17

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