JP2000340529A5 - - Google Patents

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Publication number
JP2000340529A5
JP2000340529A5 JP1999152849A JP15284999A JP2000340529A5 JP 2000340529 A5 JP2000340529 A5 JP 2000340529A5 JP 1999152849 A JP1999152849 A JP 1999152849A JP 15284999 A JP15284999 A JP 15284999A JP 2000340529 A5 JP2000340529 A5 JP 2000340529A5
Authority
JP
Japan
Prior art keywords
dummy wiring
layer dummy
wiring pattern
semiconductor device
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1999152849A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000340529A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP11152849A priority Critical patent/JP2000340529A/ja
Priority claimed from JP11152849A external-priority patent/JP2000340529A/ja
Priority to US09/457,525 priority patent/US6335560B1/en
Publication of JP2000340529A publication Critical patent/JP2000340529A/ja
Publication of JP2000340529A5 publication Critical patent/JP2000340529A5/ja
Pending legal-status Critical Current

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JP11152849A 1999-05-31 1999-05-31 半導体装置 Pending JP2000340529A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP11152849A JP2000340529A (ja) 1999-05-31 1999-05-31 半導体装置
US09/457,525 US6335560B1 (en) 1999-05-31 1999-12-09 Semiconductor device having a mark section and a dummy pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11152849A JP2000340529A (ja) 1999-05-31 1999-05-31 半導体装置

Publications (2)

Publication Number Publication Date
JP2000340529A JP2000340529A (ja) 2000-12-08
JP2000340529A5 true JP2000340529A5 (https=) 2006-06-29

Family

ID=15549484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11152849A Pending JP2000340529A (ja) 1999-05-31 1999-05-31 半導体装置

Country Status (2)

Country Link
US (1) US6335560B1 (https=)
JP (1) JP2000340529A (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3065309B1 (ja) 1999-03-11 2000-07-17 沖電気工業株式会社 半導体装置の製造方法
KR100500934B1 (ko) * 2000-05-31 2005-07-14 주식회사 하이닉스반도체 웨이퍼 가장자리의 과도 연마를 방지할 수 있는 반도체소자 제조 방법
JP3539373B2 (ja) * 2000-09-06 2004-07-07 セイコーエプソン株式会社 半導体装置
JP2002158278A (ja) * 2000-11-20 2002-05-31 Hitachi Ltd 半導体装置およびその製造方法ならびに設計方法
WO2003025982A1 (en) * 2001-09-17 2003-03-27 Advion Biosciences, Inc. Uniform patterning for deep reactive ion etching
JP2003188111A (ja) * 2001-12-20 2003-07-04 Mitsubishi Electric Corp 半導体装置の製造方法およびフォトマスク作成方法
JP4136684B2 (ja) * 2003-01-29 2008-08-20 Ｎｅｃエレクトロニクス株式会社 半導体装置及びそのダミーパターンの配置方法
WO2004097916A1 (ja) 2003-04-30 2004-11-11 Fujitsu Limited 半導体装置の製造方法、半導体ウエハおよび半導体装置
JP2005136135A (ja) * 2003-10-30 2005-05-26 Oki Electric Ind Co Ltd 半導体装置、及び半導体装置の製造方法
TWI228226B (en) * 2003-11-21 2005-02-21 Taiwan Semiconductor Mfg Dummy pattern layout method for improving film planarization
US7304323B2 (en) * 2003-12-11 2007-12-04 Nanya Technology Corporation Test mask structure
US7202550B2 (en) * 2004-06-01 2007-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated stress relief pattern and registration structure
JP4222979B2 (ja) 2004-07-28 2009-02-12 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP2009289942A (ja) * 2008-05-29 2009-12-10 Micronics Japan Co Ltd 多層配線基板
JP2010267933A (ja) 2009-05-18 2010-11-25 Elpida Memory Inc ダミーパターンの配置方法及びダミーパターンを備えた半導体装置
US9646958B2 (en) * 2010-03-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits including dummy structures and methods of forming the same
US8423945B2 (en) * 2010-05-18 2013-04-16 International Business Machines Corporation Methods and systems to meet technology pattern density requirements of semiconductor fabrication processes
JP6054596B2 (ja) * 2011-05-31 2016-12-27 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置および半導体装置設計方法
CN112951806B (zh) * 2021-02-23 2023-12-01 长江存储科技有限责任公司 半导体结构和半导体结构的台阶高度的确定方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59186342A (ja) * 1983-04-06 1984-10-23 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6015944A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd 半導体装置
JPS61193454A (ja) * 1985-02-20 1986-08-27 Mitsubishi Electric Corp 半導体装置
JPH0644669B2 (ja) * 1987-10-31 1994-06-08 イビデン株式会社 表面実装部品搭載用プリント配線板
JPH01260818A (ja) * 1988-04-12 1989-10-18 Mitsubishi Electric Corp アライメントマークの付設構造
TW299458B (https=) * 1994-11-10 1997-03-01 Intel Corp
KR100190048B1 (ko) * 1996-06-25 1999-06-01 윤종용 반도체 소자의 소자 분리 방법
JPH10189497A (ja) * 1996-12-25 1998-07-21 Toshiba Corp 半導体装置及びその製造方法
JP3638778B2 (ja) * 1997-03-31 2005-04-13 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
JPH1116999A (ja) * 1997-06-27 1999-01-22 Hitachi Ltd 半導体集積回路装置およびその製造方法ならびにその設計方法

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