JP2000268596A - 半導体記憶装置 - Google Patents

半導体記憶装置

Info

Publication number
JP2000268596A
JP2000268596A JP6689399A JP6689399A JP2000268596A JP 2000268596 A JP2000268596 A JP 2000268596A JP 6689399 A JP6689399 A JP 6689399A JP 6689399 A JP6689399 A JP 6689399A JP 2000268596 A JP2000268596 A JP 2000268596A
Authority
JP
Japan
Prior art keywords
program
address
circuit
memory cell
electric fuse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6689399A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000268596A5 (enExample
Inventor
Tsukasa Oishi
司 大石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6689399A priority Critical patent/JP2000268596A/ja
Priority to US09/376,060 priority patent/US6205064B1/en
Publication of JP2000268596A publication Critical patent/JP2000268596A/ja
Priority to US09/765,427 priority patent/US6333878B2/en
Publication of JP2000268596A5 publication Critical patent/JP2000268596A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/838—Masking faults in memories by using spares or by reconfiguring using programmable devices with substitution of defective spares
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
JP6689399A 1999-03-12 1999-03-12 半導体記憶装置 Pending JP2000268596A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP6689399A JP2000268596A (ja) 1999-03-12 1999-03-12 半導体記憶装置
US09/376,060 US6205064B1 (en) 1999-03-12 1999-08-17 Semiconductor memory device having program circuit
US09/765,427 US6333878B2 (en) 1999-03-12 2001-01-22 Semiconductor memory device having program circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6689399A JP2000268596A (ja) 1999-03-12 1999-03-12 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2000268596A true JP2000268596A (ja) 2000-09-29
JP2000268596A5 JP2000268596A5 (enExample) 2006-02-23

Family

ID=13329063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6689399A Pending JP2000268596A (ja) 1999-03-12 1999-03-12 半導体記憶装置

Country Status (2)

Country Link
US (2) US6205064B1 (enExample)
JP (1) JP2000268596A (enExample)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001006389A (ja) * 1999-06-17 2001-01-12 Fujitsu Ltd 半導体記憶装置
KR100376265B1 (ko) * 1999-12-29 2003-03-17 주식회사 하이닉스반도체 모스 구조의 안티퓨즈를 이용한 메모리 리페어 회로
KR100649970B1 (ko) * 2000-12-30 2006-11-27 주식회사 하이닉스반도체 리던던시 회로
JP2006338854A (ja) * 2005-05-30 2006-12-14 Hynix Semiconductor Inc テスト制御回路を有する半導体メモリ装置
JP2008010765A (ja) * 2006-06-30 2008-01-17 Fujitsu Ltd 半導体装置及びその製造方法
JP2010526396A (ja) * 2007-04-26 2010-07-29 アギア システムズ インコーポレーテッド ヒューズ焼付け状態機械及びヒューズダウンロード状態機械に基づく内蔵メモリ修理方法
US7940583B2 (en) 2008-02-08 2011-05-10 Elpida Memory, Inc. Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address
WO2011055492A1 (ja) * 2009-11-09 2011-05-12 パナソニック株式会社 半導体記憶装置
US8116156B2 (en) 2008-02-08 2012-02-14 Elpida Memory, Inc. Semiconductor memory device

Families Citing this family (32)

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KR100344819B1 (ko) * 1999-09-20 2002-07-19 주식회사 하이닉스반도체 불휘발성 강유전체 메모리 장치 및 그 구동회로
US6479310B1 (en) * 2000-01-03 2002-11-12 Motorola, Inc. Method for testing a semiconductor integrated circuit device
US8164362B2 (en) * 2000-02-02 2012-04-24 Broadcom Corporation Single-ended sense amplifier with sample-and-hold reference
US6603712B2 (en) * 2000-02-02 2003-08-05 Broadcom Corporation High precision delay measurement circuit
DE10037794A1 (de) * 2000-08-03 2002-02-21 Infineon Technologies Ag Verfahren und Vorrichtung zum Testen einer integrierten Schaltung, zu testende integrierte Schaltung, und Wafer mit einer Vielzahl von zu testenden integrierten Schaltungen
DE10119142B4 (de) * 2001-04-19 2008-08-28 Qimonda Ag Halbleiterbaustein mit einer Vorrichtung zum Reparieren von fehlerhaften Adressen
JP4790158B2 (ja) 2001-06-11 2011-10-12 ルネサスエレクトロニクス株式会社 半導体装置
US6973605B1 (en) * 2001-06-15 2005-12-06 Artisan Components, Inc. System and method for assured built in self repair of memories
DE10154812B4 (de) * 2001-11-08 2010-04-15 Qimonda Ag Schaltung zum Einstellen einer Signallaufzeit eines Signals auf einer Signalleitung
DE10164032B4 (de) * 2001-12-28 2008-10-23 Qimonda Ag Verfahren zum Aktivieren von Sicherungseinheiten in elektronischen Schaltungseinrichtungen
KR100429237B1 (ko) * 2002-02-21 2004-04-29 주식회사 하이닉스반도체 불휘발성 강유전체 메모리 장치의 리페어 방법 및 회로
KR100583107B1 (ko) * 2002-12-21 2006-05-23 주식회사 하이닉스반도체 리페어 회로
JP4254333B2 (ja) * 2003-05-01 2009-04-15 ソニー株式会社 半導体記憶装置およびそのセルフリペア方法
CN100375195C (zh) * 2003-10-24 2008-03-12 上海宏力半导体制造有限公司 光刻式只读存储器的感测放大器
JP4439950B2 (ja) * 2004-03-10 2010-03-24 富士通マイクロエレクトロニクス株式会社 半導体集積回路
DE102004040750B4 (de) * 2004-08-23 2008-03-27 Qimonda Ag Speicherzellenanordnung mit Speicherzellen vom CBRAM-Typ und Verfahren zum Programmieren derselben
KR100555578B1 (ko) * 2004-11-30 2006-03-03 삼성전자주식회사 디커플링 커패시터를 포함하는 반도체 메모리 소자
US7266737B2 (en) * 2005-07-13 2007-09-04 International Business Machines Corporation Method for enabling scan of defective ram prior to repair
JP2008042054A (ja) * 2006-08-09 2008-02-21 Matsushita Electric Ind Co Ltd 電気ヒューズ装置
US7889587B2 (en) * 2006-12-06 2011-02-15 Intel Corporation Fuse programming schemes for robust yield
WO2008090670A1 (ja) * 2007-01-25 2008-07-31 Sharp Kabushiki Kaisha パルス出力回路、それを用いた表示装置の駆動回路、表示装置、およびパルス出力方法
KR101003150B1 (ko) * 2009-05-14 2010-12-21 주식회사 하이닉스반도체 어드레스 시프트 회로 및 방법
US8194489B2 (en) * 2010-01-21 2012-06-05 International Business Machines Corporation Paired programmable fuses
JP2011233631A (ja) * 2010-04-26 2011-11-17 Elpida Memory Inc 半導体装置
US8719648B2 (en) 2011-07-27 2014-05-06 International Business Machines Corporation Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture
US8467260B2 (en) 2011-08-05 2013-06-18 International Business Machines Corporation Structure and method for storing multiple repair pass data into a fusebay
US8484543B2 (en) 2011-08-08 2013-07-09 International Business Machines Corporation Fusebay controller structure, system, and method
US8537627B2 (en) 2011-09-01 2013-09-17 International Business Machines Corporation Determining fusebay storage element usage
KR20150006167A (ko) * 2013-07-08 2015-01-16 에스케이하이닉스 주식회사 반도체 시스템 및 그 리페어 방법
KR102152690B1 (ko) * 2014-06-26 2020-09-07 에스케이하이닉스 주식회사 래치 회로 및 이를 포함하는 반도체 장치
US9691446B2 (en) 2015-09-11 2017-06-27 Kabushiki Kaisha Toshiba Memory device
EP4012709B1 (en) * 2020-09-14 2024-01-03 Changxin Memory Technologies, Inc. Semiconductor memory

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5206583A (en) * 1991-08-20 1993-04-27 International Business Machines Corporation Latch assisted fuse testing for customized integrated circuits
JP3553138B2 (ja) * 1994-07-14 2004-08-11 株式会社ルネサステクノロジ 半導体記憶装置
JP2629645B2 (ja) * 1995-04-20 1997-07-09 日本電気株式会社 半導体記憶装置
KR970001564U (ko) * 1995-06-21 1997-01-21 자동차용 후부차체의 보강구조
US5574689A (en) * 1995-07-11 1996-11-12 Micron Technology, Inc. Address comparing for non-precharged redundancy address matching
US5631862A (en) 1996-03-05 1997-05-20 Micron Technology, Inc. Self current limiting antifuse circuit
JP2882369B2 (ja) * 1996-06-27 1999-04-12 日本電気株式会社 半導体記憶装置
JP2000235800A (ja) * 1999-02-12 2000-08-29 Mitsubishi Electric Corp 半導体記憶装置

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001006389A (ja) * 1999-06-17 2001-01-12 Fujitsu Ltd 半導体記憶装置
KR100376265B1 (ko) * 1999-12-29 2003-03-17 주식회사 하이닉스반도체 모스 구조의 안티퓨즈를 이용한 메모리 리페어 회로
KR100649970B1 (ko) * 2000-12-30 2006-11-27 주식회사 하이닉스반도체 리던던시 회로
JP2006338854A (ja) * 2005-05-30 2006-12-14 Hynix Semiconductor Inc テスト制御回路を有する半導体メモリ装置
JP2008010765A (ja) * 2006-06-30 2008-01-17 Fujitsu Ltd 半導体装置及びその製造方法
JP2010526396A (ja) * 2007-04-26 2010-07-29 アギア システムズ インコーポレーテッド ヒューズ焼付け状態機械及びヒューズダウンロード状態機械に基づく内蔵メモリ修理方法
US7940583B2 (en) 2008-02-08 2011-05-10 Elpida Memory, Inc. Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address
US8116156B2 (en) 2008-02-08 2012-02-14 Elpida Memory, Inc. Semiconductor memory device
WO2011055492A1 (ja) * 2009-11-09 2011-05-12 パナソニック株式会社 半導体記憶装置
US8446751B2 (en) 2009-11-09 2013-05-21 Panasonic Corporation Semiconductor memory device
JP5462863B2 (ja) * 2009-11-09 2014-04-02 パナソニック株式会社 半導体記憶装置

Also Published As

Publication number Publication date
US20010014040A1 (en) 2001-08-16
US6333878B2 (en) 2001-12-25
US6205064B1 (en) 2001-03-20

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