ITMI923001A0 - Dispositivo di memoria a semiconduttore e suo metodo di funzionamento - Google Patents

Dispositivo di memoria a semiconduttore e suo metodo di funzionamento

Info

Publication number
ITMI923001A0
ITMI923001A0 IT92MI3001A ITMI923001A ITMI923001A0 IT MI923001 A0 ITMI923001 A0 IT MI923001A0 IT 92MI3001 A IT92MI3001 A IT 92MI3001A IT MI923001 A ITMI923001 A IT MI923001A IT MI923001 A0 ITMI923001 A0 IT MI923001A0
Authority
IT
Italy
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Application number
IT92MI3001A
Other languages
English (en)
Inventor
Kenji Tokami
Yoshinaga Inoue
Original Assignee
Mitsubishi Kenki
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Kenki filed Critical Mitsubishi Kenki
Publication of ITMI923001A0 publication Critical patent/ITMI923001A0/it
Publication of ITMI923001A1 publication Critical patent/ITMI923001A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
IT003001A 1992-07-09 1992-12-31 Dispositivo di memoria a semiconduttore e suo metodo di funzionamento ITMI923001A1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4182260A JPH0628846A (ja) 1992-07-09 1992-07-09 半導体記憶装置

Publications (2)

Publication Number Publication Date
ITMI923001A0 true ITMI923001A0 (it) 1992-12-31
ITMI923001A1 ITMI923001A1 (it) 1994-07-01

Family

ID=16115144

Family Applications (1)

Application Number Title Priority Date Filing Date
IT003001A ITMI923001A1 (it) 1992-07-09 1992-12-31 Dispositivo di memoria a semiconduttore e suo metodo di funzionamento

Country Status (5)

Country Link
US (1) US5430686A (it)
JP (1) JPH0628846A (it)
KR (1) KR940006138A (it)
DE (1) DE4235951C2 (it)
IT (1) ITMI923001A1 (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0778106A (ja) * 1993-09-08 1995-03-20 Hitachi Ltd データ処理システム
US5838603A (en) 1994-10-11 1998-11-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same, memory core chip and memory peripheral circuit chip
US5699315A (en) * 1995-03-24 1997-12-16 Texas Instruments Incorporated Data processing with energy-efficient, multi-divided module memory architectures
KR0172781B1 (ko) * 1995-12-31 1999-03-30 김주용 반도체 메모리의 내부 어드레스 발생장치
US5680365A (en) * 1996-05-16 1997-10-21 Mitsubishi Semiconductor America, Inc. Shared dram I/O databus for high speed operation
US5802395A (en) * 1996-07-08 1998-09-01 International Business Machines Corporation High density memory modules with improved data bus performance
US5959929A (en) 1997-12-29 1999-09-28 Micron Technology, Inc. Method for writing to multiple banks of a memory device
KR100296452B1 (ko) * 1997-12-29 2001-10-24 윤종용 데이터 입력 버퍼들을 구비한 동기식 반도체 메모리 장치
JP2003059264A (ja) * 2001-08-08 2003-02-28 Hitachi Ltd 半導体記憶装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57150190A (en) * 1981-02-27 1982-09-16 Hitachi Ltd Monolithic storage device
JPS59139646A (ja) * 1983-01-31 1984-08-10 Hitachi Micro Comput Eng Ltd 半導体集積回路装置
JPS6018894A (ja) * 1983-07-12 1985-01-30 Fujitsu Ltd 半導体装置
EP0262413B1 (en) * 1986-09-04 1992-07-22 Fujitsu Limited Memory device employing address multiplexing
US4870620A (en) * 1987-01-06 1989-09-26 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory device with internal refresh
JPS63200556A (ja) * 1987-02-16 1988-08-18 Nec Corp 半導体集積回路のレイアウト法
DE3884492T2 (de) * 1987-07-15 1994-02-17 Hitachi Ltd Integrierte Halbleiterschaltungsanordnung.
JPS6457495A (en) * 1987-08-28 1989-03-03 Hitachi Ltd Semiconductor memory device
JP2575449B2 (ja) * 1988-02-18 1997-01-22 株式会社東芝 半導体メモリ装置
JPH0221490A (ja) * 1988-07-07 1990-01-24 Oki Electric Ind Co Ltd ダイナミック・ランダム・アクセス・メモリ
JP2646032B2 (ja) * 1989-10-14 1997-08-25 三菱電機株式会社 Ｌｉｆｏ方式の半導体記憶装置およびその制御方法
JP2777247B2 (ja) * 1990-01-16 1998-07-16 三菱電機株式会社 半導体記憶装置およびキャッシュシステム
JPH03232196A (ja) * 1990-02-07 1991-10-16 Toshiba Corp 半導体記憶装置
JP2601951B2 (ja) * 1991-01-11 1997-04-23 株式会社東芝 半導体集積回路
JP3115623B2 (ja) * 1991-02-25 2000-12-11 株式会社日立製作所 スタティック型ｒａｍ

Also Published As

Publication number Publication date
ITMI923001A1 (it) 1994-07-01
DE4235951C2 (de) 1995-06-29
DE4235951A1 (de) 1994-01-13
KR940006138A (ko) 1994-03-23
US5430686A (en) 1995-07-04
JPH0628846A (ja) 1994-02-04

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