ITMI911952A1 - Dispositivo semiconduttore e metodo per la sua fabbricazione - Google Patents

Dispositivo semiconduttore e metodo per la sua fabbricazione

Info

Publication number
ITMI911952A1
ITMI911952A1 IT001952A ITMI911952A ITMI911952A1 IT MI911952 A1 ITMI911952 A1 IT MI911952A1 IT 001952 A IT001952 A IT 001952A IT MI911952 A ITMI911952 A IT MI911952A IT MI911952 A1 ITMI911952 A1 IT MI911952A1
Authority
IT
Italy
Prior art keywords
manufacture
semiconductive device
semiconductive
Prior art date
Application number
IT001952A
Other languages
English (en)
Inventor
Dong Jun Kim
Jun Eui Song
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI911952A0 publication Critical patent/ITMI911952A0/it
Publication of ITMI911952A1 publication Critical patent/ITMI911952A1/it
Application granted granted Critical
Publication of IT1251787B publication Critical patent/IT1251787B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/009—Bi-MOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
ITMI911952A 1991-04-09 1991-07-15 Dispositivo semiconduttore e metodo per la sua fabbricazione IT1251787B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910005632A KR940009357B1 (ko) 1991-04-09 1991-04-09 반도체 장치 및 그 제조방법

Publications (3)

Publication Number Publication Date
ITMI911952A0 ITMI911952A0 (it) 1991-07-15
ITMI911952A1 true ITMI911952A1 (it) 1993-01-15
IT1251787B IT1251787B (it) 1995-05-26

Family

ID=19313038

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI911952A IT1251787B (it) 1991-04-09 1991-07-15 Dispositivo semiconduttore e metodo per la sua fabbricazione

Country Status (6)

Country Link
US (2) US5105252A (it)
JP (1) JPH04324973A (it)
KR (1) KR940009357B1 (it)
DE (1) DE4123436C2 (it)
FR (1) FR2675311B1 (it)
IT (1) IT1251787B (it)

Families Citing this family (34)

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Publication number Priority date Publication date Assignee Title
JP3057757B2 (ja) * 1990-11-29 2000-07-04 日産自動車株式会社 トランジスタ
JP2642523B2 (ja) * 1991-03-19 1997-08-20 株式会社東芝 電荷結合素子を持つ半導体集積回路装置の製造方法
JP2861624B2 (ja) * 1992-05-13 1999-02-24 日本電気株式会社 半導体装置の製造方法
KR0127282B1 (ko) * 1992-05-18 1998-04-02 도요다 요시또시 반도체 장치
US5559044A (en) * 1992-09-21 1996-09-24 Siliconix Incorporated BiCDMOS process technology
JPH0758212A (ja) * 1993-08-19 1995-03-03 Sony Corp Ｃｍｏｓ集積回路
US5472887A (en) * 1993-11-09 1995-12-05 Texas Instruments Incorporated Method of fabricating semiconductor device having high-and low-voltage MOS transistors
KR100331127B1 (ko) * 1994-02-15 2002-10-18 내셔널 세미콘덕터 코포레이션 표준cmos공정용고전압cmos트랜지스터
US5455189A (en) * 1994-02-28 1995-10-03 National Semiconductor Corporation Method of forming BICMOS structures
KR0144959B1 (ko) * 1994-05-17 1998-07-01 김광호 반도체장치 및 제조방법
JP2981717B2 (ja) * 1994-09-02 1999-11-22 セイコーインスツルメンツ株式会社 半導体集積回路装置
US5494843A (en) * 1995-06-28 1996-02-27 Taiwan Semiconductor Manufacturing Co. Method for forming MOSFET devices
US6245604B1 (en) 1996-01-16 2001-06-12 Micron Technology Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits
US5882993A (en) 1996-08-19 1999-03-16 Advanced Micro Devices, Inc. Integrated circuit with differing gate oxide thickness and process for making same
US6033943A (en) * 1996-08-23 2000-03-07 Advanced Micro Devices, Inc. Dual gate oxide thickness integrated circuit and process for making same
US5770880A (en) * 1996-09-03 1998-06-23 Harris Corporation P-collector H.V. PMOS switch VT adjusted source/drain
US6010929A (en) * 1996-12-11 2000-01-04 Texas Instruments Incorporated Method for forming high voltage and low voltage transistors on the same substrate
JP3077742B2 (ja) * 1997-03-03 2000-08-14 日本電気株式会社 半導体装置及びその製造方法
JP4014708B2 (ja) * 1997-08-21 2007-11-28 株式会社ルネサステクノロジ 半導体集積回路装置の設計方法
US5962914A (en) * 1998-01-14 1999-10-05 Advanced Micro Devices, Inc. Reduced bird's beak field oxidation process using nitrogen implanted into active region
US6531364B1 (en) 1998-08-05 2003-03-11 Advanced Micro Devices, Inc. Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer
US6265752B1 (en) * 1999-05-25 2001-07-24 Taiwan Semiconductor Manufacturing, Co., Inc. Method of forming a HVNMOS with an N+ buried layer combined with N well and a structure of the same
JP3348782B2 (ja) 1999-07-22 2002-11-20 日本電気株式会社 半導体装置の製造方法
DE69942418D1 (de) * 1999-11-19 2010-07-08 St Microelectronics Srl Herstellungsverfahren für elektronische Bauelemente mit Hochspannungs-MOS- und EEPROM-Transistoren
US7019377B2 (en) * 2002-12-17 2006-03-28 Micrel, Inc. Integrated circuit including high voltage devices and low voltage devices
US20060122635A1 (en) * 2004-12-03 2006-06-08 Naegeli Chad D Storage system for bioabsorbable fasteners
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
KR100741882B1 (ko) * 2005-12-29 2007-07-23 동부일렉트로닉스 주식회사 고전압 소자 및 그 제조방법
KR100917216B1 (ko) * 2007-02-02 2009-09-16 삼성전자주식회사 반도체 소자 및 그 형성방법
KR100752591B1 (ko) * 2007-07-06 2007-08-29 (주)위즈덤 세미컨덕터 Ｓｍｐｓ 소자 및 그 제조방법
US9214457B2 (en) 2011-09-20 2015-12-15 Alpha & Omega Semiconductor Incorporated Method of integrating high voltage devices
CN102637725B (zh) * 2012-04-26 2014-07-16 杭州士兰集成电路有限公司 采用Bipolar低压工艺实现的器件及其制造方法
CN108847423B (zh) 2018-05-30 2022-10-21 矽力杰半导体技术(杭州)有限公司 半导体器件及其制造方法
CN111668186A (zh) 2020-06-08 2020-09-15 矽力杰半导体技术(杭州)有限公司 半导体器件及其制造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4403395A (en) * 1979-02-15 1983-09-13 Texas Instruments Incorporated Monolithic integration of logic, control and high voltage interface circuitry
JPS5864060A (ja) * 1981-10-13 1983-04-16 Toshiba Corp 半導体装置の製造方法
US4697202A (en) * 1984-02-02 1987-09-29 Sri International Integrated circuit having dislocation free substrate
JPH0618255B2 (ja) * 1984-04-04 1994-03-09 株式会社東芝 半導体装置
FR2571178B1 (fr) * 1984-09-28 1986-11-21 Thomson Csf Structure de circuit integre comportant des transistors cmos a tenue en tension elevee, et son procede de fabrication
JPS61263261A (ja) * 1985-05-17 1986-11-21 Nec Corp Ｍｏｓ型半導体素子の製造方法
JPH0671067B2 (ja) * 1985-11-20 1994-09-07 株式会社日立製作所 半導体装置
JPH0628266B2 (ja) * 1986-07-09 1994-04-13 株式会社日立製作所 半導体装置の製造方法
JPS63283152A (ja) * 1987-05-15 1988-11-21 Toshiba Corp 半導体装置およびその製造方法
US4764482A (en) * 1986-11-21 1988-08-16 General Electric Company Method of fabricating an integrated circuit containing bipolar and MOS transistors
JPH01110760A (ja) * 1987-06-25 1989-04-27 Fuji Electric Co Ltd ＢｉＣＭＯＳ半導体装置
JPH01112763A (ja) * 1987-10-27 1989-05-01 Sharp Corp 半導体装置
JPH01140759A (ja) * 1987-11-27 1989-06-01 Nec Corp Ｂｉ−ＭＯＳ半導体装置
JPH02102569A (ja) * 1988-10-12 1990-04-16 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
JPH02112272A (ja) * 1988-10-21 1990-04-24 Olympus Optical Co Ltd 半導体装置
JPH02139963A (ja) * 1988-11-21 1990-05-29 Olympus Optical Co Ltd Ｃｍｏｓデバイス
US5034337A (en) * 1989-02-10 1991-07-23 Texas Instruments Incorporated Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices
JPH0770703B2 (ja) * 1989-05-22 1995-07-31 株式会社東芝 電荷転送デバイスを含む半導体装置およびその製造方法
US4908328A (en) * 1989-06-06 1990-03-13 National Semiconductor Corporation High voltage power IC process
IT1235843B (it) * 1989-06-14 1992-11-03 Sgs Thomson Microelectronics Dispositivo integrato contenente strutture di potenza formate con transistori ldmos complementari, strutture cmos e pnp verticali con aumentata capacita' di supportare un'alta tensione di alimentazione.

Also Published As

Publication number Publication date
FR2675311B1 (fr) 1996-03-08
JPH04324973A (ja) 1992-11-13
KR920020598A (ko) 1992-11-21
FR2675311A1 (fr) 1992-10-16
ITMI911952A0 (it) 1991-07-15
IT1251787B (it) 1995-05-26
KR940009357B1 (ko) 1994-10-07
DE4123436C2 (de) 1995-09-07
US5158463A (en) 1992-10-27
US5105252A (en) 1992-04-14
DE4123436A1 (de) 1992-10-15

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970730