DE69942418D1 - Herstellungsverfahren für elektronische Bauelemente mit Hochspannungs-MOS- und EEPROM-Transistoren - Google Patents

Herstellungsverfahren für elektronische Bauelemente mit Hochspannungs-MOS- und EEPROM-Transistoren

Info

Publication number
DE69942418D1
DE69942418D1 DE69942418T DE69942418T DE69942418D1 DE 69942418 D1 DE69942418 D1 DE 69942418D1 DE 69942418 T DE69942418 T DE 69942418T DE 69942418 T DE69942418 T DE 69942418T DE 69942418 D1 DE69942418 D1 DE 69942418D1
Authority
DE
Germany
Prior art keywords
electronic device
high voltage
fabrication process
device fabrication
voltage mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69942418T
Other languages
English (en)
Inventor
Bruno Vajana
Matteo Patelmo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69942418D1 publication Critical patent/DE69942418D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE69942418T 1999-11-19 1999-11-19 Herstellungsverfahren für elektronische Bauelemente mit Hochspannungs-MOS- und EEPROM-Transistoren Expired - Lifetime DE69942418D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP99830717A EP1102319B1 (de) 1999-11-19 1999-11-19 Herstellungsverfahren für elektronische Bauelemente mit Hochspannungs-MOS- und EEPROM-Transistoren

Publications (1)

Publication Number Publication Date
DE69942418D1 true DE69942418D1 (de) 2010-07-08

Family

ID=8243673

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69942418T Expired - Lifetime DE69942418D1 (de) 1999-11-19 1999-11-19 Herstellungsverfahren für elektronische Bauelemente mit Hochspannungs-MOS- und EEPROM-Transistoren

Country Status (3)

Country Link
US (1) US6501147B1 (de)
EP (1) EP1102319B1 (de)
DE (1) DE69942418D1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6580135B2 (en) * 2001-06-18 2003-06-17 Macronix International Co., Ltd. Silicon nitride read only memory structure and method of programming and erasure
DE10201303A1 (de) * 2002-01-15 2003-07-31 Infineon Technologies Ag Nichtflüchtige Zweitransistor-Halbleiterspeicherzelle sowie zugehöriges Herstellungsverfahren
DE10206375A1 (de) * 2002-02-15 2003-06-26 Infineon Technologies Ag Integrierte, abstimmbare Kapazität
US8692310B2 (en) 2009-02-09 2014-04-08 Spansion Llc Gate fringing effect based channel formation for semiconductor device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH657712A5 (de) * 1978-03-08 1986-09-15 Hitachi Ltd Referenzspannungserzeuger.
JPS5887858A (ja) * 1981-11-20 1983-05-25 Hitachi Ltd 相補型絶縁ゲ−ト電界効果半導体装置
US5024960A (en) * 1987-06-16 1991-06-18 Texas Instruments Incorporated Dual LDD submicron CMOS process for making low and high voltage transistors with common gate
US5047358A (en) * 1989-03-17 1991-09-10 Delco Electronics Corporation Process for forming high and low voltage CMOS transistors on a single integrated circuit chip
JPH03177065A (ja) * 1989-12-06 1991-08-01 Kawasaki Steel Corp 半導体装置およびその製造方法
KR940009357B1 (ko) * 1991-04-09 1994-10-07 삼성전자주식회사 반도체 장치 및 그 제조방법
JP2819972B2 (ja) * 1992-11-10 1998-11-05 日本電気株式会社 半導体装置の製造方法
US5472887A (en) * 1993-11-09 1995-12-05 Texas Instruments Incorporated Method of fabricating semiconductor device having high-and low-voltage MOS transistors
JPH07273212A (ja) * 1994-03-31 1995-10-20 Toshiba Corp 半導体装置及びその製造方法
JPH07335883A (ja) * 1994-06-15 1995-12-22 Toshiba Corp 半導体装置の製造方法
JPH10189762A (ja) * 1996-12-20 1998-07-21 Nec Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP1102319B1 (de) 2010-05-26
EP1102319A1 (de) 2001-05-23
US6501147B1 (en) 2002-12-31

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