IT9048190A0 - "metodo per collaudo in parallelo su piu' bit in un dispositivo di memoria a semiconduttori" - Google Patents
"metodo per collaudo in parallelo su piu' bit in un dispositivo di memoria a semiconduttori"Info
- Publication number
- IT9048190A0 IT9048190A0 IT9048190A IT4819090A IT9048190A0 IT 9048190 A0 IT9048190 A0 IT 9048190A0 IT 9048190 A IT9048190 A IT 9048190A IT 4819090 A IT4819090 A IT 4819090A IT 9048190 A0 IT9048190 A0 IT 9048190A0
- Authority
- IT
- Italy
- Prior art keywords
- memory device
- semiconductor memory
- multiple bits
- parallel testing
- testing
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
- G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/34—Accessing multiple bits simultaneously
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900008924A KR930008417B1 (ko) | 1990-06-18 | 1990-06-18 | 반도체 메모리 장치의 다중 비트 병렬 테스트방법 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| IT9048190A0 true IT9048190A0 (it) | 1990-07-31 |
| IT9048190A1 IT9048190A1 (it) | 1992-01-31 |
| IT1241525B IT1241525B (it) | 1994-01-17 |
Family
ID=19300202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT48190A IT1241525B (it) | 1990-06-18 | 1990-07-31 | "metodo per collaudo in parallelo su piu' bit in un dispositivo di memoria a semiconduttori". |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5077689A (it) |
| JP (1) | JP3025519B2 (it) |
| KR (1) | KR930008417B1 (it) |
| CN (1) | CN1025077C (it) |
| DE (1) | DE4023015C1 (it) |
| FR (1) | FR2663450B1 (it) |
| GB (1) | GB2245393B (it) |
| IT (1) | IT1241525B (it) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5675544A (en) * | 1990-06-25 | 1997-10-07 | Texas Instruments Incorporated | Method and apparatus for parallel testing of memory circuits |
| KR950001293B1 (ko) * | 1992-04-22 | 1995-02-15 | 삼성전자주식회사 | 반도체 메모리칩의 병렬테스트 회로 |
| JPH06295599A (ja) * | 1993-04-09 | 1994-10-21 | Nec Corp | 半導体記憶装置 |
| KR960008824B1 (en) * | 1993-11-17 | 1996-07-05 | Samsung Electronics Co Ltd | Multi bit test circuit and method of semiconductor memory device |
| KR0137846B1 (ko) * | 1994-03-24 | 1998-06-15 | 문정환 | 반도체 기억장치의 멀티비트 테스트회로 |
| KR0172533B1 (ko) * | 1995-10-18 | 1999-03-30 | 김주용 | 플래쉬 메모리 장치 |
| US5592425A (en) * | 1995-12-20 | 1997-01-07 | Intel Corporation | Method and apparatus for testing a memory where data is passed through the memory for comparison with data read from the memory |
| US5905744A (en) * | 1997-09-30 | 1999-05-18 | Lsi Logic Corporation | Test mode for multifunction PCI device |
| JP3322303B2 (ja) * | 1998-10-28 | 2002-09-09 | 日本電気株式会社 | 半導体記憶装置 |
| KR100339502B1 (ko) | 1999-06-02 | 2002-05-31 | 윤종용 | 다수개의 데이터 라인을 구분되게 테스트하는 통합 데이터 라인 테스트 회로 및 이를 이용하는 테스트 방법 |
| KR100295691B1 (ko) * | 1999-06-04 | 2001-07-12 | 김영환 | 디램의 오픈 테스트용 테스트모드회로 |
| JP3484388B2 (ja) * | 2000-02-08 | 2004-01-06 | 日本電気株式会社 | 半導体記憶装置 |
| KR100346447B1 (ko) * | 2000-06-30 | 2002-07-27 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 병렬 테스트 장치 |
| KR100546308B1 (ko) * | 2002-12-13 | 2006-01-26 | 삼성전자주식회사 | 데이터 독출 능력이 향상된 반도체 메모리 장치. |
| KR100699827B1 (ko) * | 2004-03-23 | 2007-03-27 | 삼성전자주식회사 | 메모리 모듈 |
| US7480195B2 (en) * | 2005-05-11 | 2009-01-20 | Micron Technology, Inc. | Internal data comparison for memory testing |
| KR100809070B1 (ko) * | 2006-06-08 | 2008-03-03 | 삼성전자주식회사 | 반도체 메모리 장치의 병렬 비트 테스트 회로 및 그 방법 |
| US9067213B2 (en) | 2008-07-02 | 2015-06-30 | Buhler Ag | Method for producing flour and/or semolina |
| CN101770967A (zh) * | 2009-01-03 | 2010-07-07 | 上海芯豪微电子有限公司 | 一种共用基底集成电路测试方法、装置和系统 |
| KR20150033374A (ko) * | 2013-09-24 | 2015-04-01 | 에스케이하이닉스 주식회사 | 반도체 시스템 및 반도체 장치 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60115099A (ja) * | 1983-11-25 | 1985-06-21 | Fujitsu Ltd | 半導体記憶装置 |
| US4686456A (en) * | 1985-06-18 | 1987-08-11 | Kabushiki Kaisha Toshiba | Memory test circuit |
| JP2523586B2 (ja) * | 1987-02-27 | 1996-08-14 | 株式会社日立製作所 | 半導体記憶装置 |
| JPH01286200A (ja) * | 1988-05-12 | 1989-11-17 | Fujitsu Ltd | 半導体メモリ装置 |
| JPH0713858B2 (ja) * | 1988-08-30 | 1995-02-15 | 三菱電機株式会社 | 半導体記憶装置 |
| KR910005306B1 (ko) * | 1988-12-31 | 1991-07-24 | 삼성전자 주식회사 | 고밀도 메모리의 테스트를 위한 병렬리드회로 |
-
1990
- 1990-06-18 KR KR1019900008924A patent/KR930008417B1/ko not_active IP Right Cessation
- 1990-07-18 FR FR9009152A patent/FR2663450B1/fr not_active Expired - Fee Related
- 1990-07-19 DE DE4023015A patent/DE4023015C1/de not_active Expired - Lifetime
- 1990-07-30 US US07/559,697 patent/US5077689A/en not_active Expired - Lifetime
- 1990-07-31 GB GB9016763A patent/GB2245393B/en not_active Expired - Fee Related
- 1990-07-31 CN CN90106619A patent/CN1025077C/zh not_active Expired - Fee Related
- 1990-07-31 IT IT48190A patent/IT1241525B/it active IP Right Grant
- 1990-07-31 JP JP02201562A patent/JP3025519B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR930008417B1 (ko) | 1993-08-31 |
| GB2245393B (en) | 1994-02-23 |
| IT1241525B (it) | 1994-01-17 |
| US5077689A (en) | 1991-12-31 |
| FR2663450A1 (fr) | 1991-12-20 |
| IT9048190A1 (it) | 1992-01-31 |
| CN1057720A (zh) | 1992-01-08 |
| JPH0448500A (ja) | 1992-02-18 |
| CN1025077C (zh) | 1994-06-15 |
| GB9016763D0 (en) | 1990-09-12 |
| FR2663450B1 (fr) | 1993-10-15 |
| JP3025519B2 (ja) | 2000-03-27 |
| DE4023015C1 (it) | 1991-12-19 |
| KR920001552A (ko) | 1992-01-30 |
| GB2245393A (en) | 1992-01-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted | ||
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970528 |