IT8424228A0 - Dispositivo di memoria a semiconduttori avente una disposizione di collegamento e di decodificazione migliorata per ridurre il ritardo dei collegamenti. - Google Patents

Dispositivo di memoria a semiconduttori avente una disposizione di collegamento e di decodificazione migliorata per ridurre il ritardo dei collegamenti.

Info

Publication number
IT8424228A0
IT8424228A0 IT8424228A IT2422884A IT8424228A0 IT 8424228 A0 IT8424228 A0 IT 8424228A0 IT 8424228 A IT8424228 A IT 8424228A IT 2422884 A IT2422884 A IT 2422884A IT 8424228 A0 IT8424228 A0 IT 8424228A0
Authority
IT
Italy
Prior art keywords
connection
memory device
semiconductor memory
decoding arrangement
reduce
Prior art date
Application number
IT8424228A
Other languages
English (en)
Other versions
IT1179531B (it
Inventor
Kazuhiko Kajigaya
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of IT8424228A0 publication Critical patent/IT8424228A0/it
Application granted granted Critical
Publication of IT1179531B publication Critical patent/IT1179531B/it

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/14Word line organisation; Word line lay-out
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00Climate change mitigation technologies for sector-wide applications
    • Y02P80/30Reducing waste in manufacturing processes; Calculations of released waste quantities

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
IT24228/84A 1983-12-23 1984-12-21 Dispositivo di memoria a semiconduttori avente una disposizione di collegamento e di decodificazione migliorata per ridurre il ritardo dei collegamenti IT1179531B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58241965A JPH0682801B2 (ja) 1983-12-23 1983-12-23 半導体記憶装置とそのレイアウト方法

Publications (2)

Publication Number Publication Date
IT8424228A0 true IT8424228A0 (it) 1984-12-21
IT1179531B IT1179531B (it) 1987-09-16

Family

ID=17082208

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24228/84A IT1179531B (it) 1983-12-23 1984-12-21 Dispositivo di memoria a semiconduttori avente una disposizione di collegamento e di decodificazione migliorata per ridurre il ritardo dei collegamenti

Country Status (7)

Country Link
US (2) US4709351A (it)
JP (1) JPH0682801B2 (it)
KR (1) KR930000761B1 (it)
DE (1) DE3447722A1 (it)
GB (1) GB2152752B (it)
HK (1) HK47990A (it)
IT (1) IT1179531B (it)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0740602B2 (ja) * 1985-09-25 1995-05-01 セイコーエプソン株式会社 半導体記憶装置
US4829351A (en) * 1987-03-16 1989-05-09 Motorola, Inc. Polysilicon pattern for a floating gate memory
US4992981A (en) * 1987-06-05 1991-02-12 International Business Machines Corporation Double-ended memory cell array using interleaved bit lines and method of fabrication therefore
US5204842A (en) * 1987-08-05 1993-04-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory with memory unit comprising a plurality of memory blocks
US5014242A (en) * 1987-12-10 1991-05-07 Hitachi, Ltd. Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit
JP2790287B2 (ja) * 1988-08-12 1998-08-27 株式会社東芝 集積回路の配置構造
EP0365876B1 (en) * 1988-10-28 1996-09-25 Texas Instruments Incorporated Decoding global drive/boot signals using local predecoders
US5117389A (en) * 1990-09-05 1992-05-26 Macronix International Co., Ltd. Flat-cell read-only-memory integrated circuit
JP3242101B2 (ja) * 1990-10-05 2001-12-25 三菱電機株式会社 半導体集積回路
US5200355A (en) * 1990-12-10 1993-04-06 Samsung Electronics Co., Ltd. Method for manufacturing a mask read only memory device
US5396100A (en) * 1991-04-05 1995-03-07 Hitachi, Ltd. Semiconductor integrated circuit device having a compact arrangement of SRAM cells
JP3186084B2 (ja) * 1991-05-24 2001-07-11 日本電気株式会社 半導体メモリー装置
JP3333352B2 (ja) * 1995-04-12 2002-10-15 株式会社東芝 半導体記憶装置
US6388314B1 (en) * 1995-08-17 2002-05-14 Micron Technology, Inc. Single deposition layer metal dynamic random access memory
US5640338A (en) * 1995-12-07 1997-06-17 Hyundai Electronics Industries Co. Ltd. Semiconductor memory device
KR100224779B1 (ko) * 1996-12-31 1999-10-15 김영환 로오 디코더 회로
US5903491A (en) 1997-06-09 1999-05-11 Micron Technology, Inc. Single deposition layer metal dynamic random access memory
JPH1126604A (ja) * 1997-07-03 1999-01-29 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3408466B2 (ja) * 1999-08-23 2003-05-19 エヌイーシーマイクロシステム株式会社 半導体記憶装置
JP2002270788A (ja) * 2001-03-14 2002-09-20 Fujitsu Ltd 半導体装置及びその製造方法
US6738301B2 (en) * 2002-08-29 2004-05-18 Micron Technology, Inc. Method and system for accelerating coupling of digital signals
JP2011242541A (ja) * 2010-05-17 2011-12-01 Panasonic Corp 半導体集積回路装置、および標準セルの端子構造
KR20120033510A (ko) * 2010-09-30 2012-04-09 주식회사 하이닉스반도체 반도체 집적 회로

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3560940A (en) * 1968-07-15 1971-02-02 Ibm Time shared interconnection apparatus
JPS5854654A (ja) * 1981-09-28 1983-03-31 Nec Corp 半導体集積回路装置
JPS602781B2 (ja) * 1982-03-03 1985-01-23 富士通株式会社 半導体記憶装置
US4618945A (en) * 1982-08-11 1986-10-21 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device

Also Published As

Publication number Publication date
DE3447722A1 (de) 1985-07-04
JPH0682801B2 (ja) 1994-10-19
KR850004877A (ko) 1985-07-27
GB2152752B (en) 1988-03-02
HK47990A (en) 1990-06-29
USRE36813E (en) 2000-08-08
GB2152752A (en) 1985-08-07
IT1179531B (it) 1987-09-16
US4709351A (en) 1987-11-24
GB8431412D0 (en) 1985-01-23
KR930000761B1 (ko) 1993-02-01
JPS60134460A (ja) 1985-07-17

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961223