DE68928589T2 - Speicheranordnung - Google Patents

Speicheranordnung

Info

Publication number
DE68928589T2
DE68928589T2 DE68928589T DE68928589T DE68928589T2 DE 68928589 T2 DE68928589 T2 DE 68928589T2 DE 68928589 T DE68928589 T DE 68928589T DE 68928589 T DE68928589 T DE 68928589T DE 68928589 T2 DE68928589 T2 DE 68928589T2
Authority
DE
Germany
Prior art keywords
storage arrangement
arrangement
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68928589T
Other languages
English (en)
Other versions
DE68928589D1 (de
Inventor
David V Kersh
Jimmie Don Childers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23005929&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE68928589(T2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE68928589D1 publication Critical patent/DE68928589D1/de
Application granted granted Critical
Publication of DE68928589T2 publication Critical patent/DE68928589T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • G11C11/4085Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/10Decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/12Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE68928589T 1988-10-28 1989-10-03 Speicheranordnung Expired - Fee Related DE68928589T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26440488A 1988-10-28 1988-10-28

Publications (2)

Publication Number Publication Date
DE68928589D1 DE68928589D1 (de) 1998-04-02
DE68928589T2 true DE68928589T2 (de) 1998-08-13

Family

ID=23005929

Family Applications (2)

Application Number Title Priority Date Filing Date
DE68927248T Expired - Fee Related DE68927248T2 (de) 1988-10-28 1989-10-03 Dekodierung von Steuer-/Initialisierungssignalen mit örtlichen Vordekodierern
DE68928589T Expired - Fee Related DE68928589T2 (de) 1988-10-28 1989-10-03 Speicheranordnung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE68927248T Expired - Fee Related DE68927248T2 (de) 1988-10-28 1989-10-03 Dekodierung von Steuer-/Initialisierungssignalen mit örtlichen Vordekodierern

Country Status (5)

Country Link
EP (2) EP0365876B1 (de)
JP (2) JP3020966B2 (de)
KR (1) KR0143237B1 (de)
DE (2) DE68927248T2 (de)
HK (1) HK1017577A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4103309A1 (de) * 1991-02-04 1992-08-06 Mikroelektronik Und Technologi Schaltungsanordnung zur ansteuerung von wortleitungen in halbleiterspeichern
KR100967106B1 (ko) * 2008-09-19 2010-07-05 주식회사 하이닉스반도체 반도체 메모리장치의 어드레스 디코딩 장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6059588A (ja) * 1983-09-12 1985-04-05 Hitachi Ltd 半導体記憶装置
US4660178A (en) * 1983-09-21 1987-04-21 Inmos Corporation Multistage decoding
JPH0682801B2 (ja) * 1983-12-23 1994-10-19 株式会社日立製作所 半導体記憶装置とそのレイアウト方法
JPS6180592A (ja) * 1984-09-26 1986-04-24 Hitachi Ltd 半導体記憶装置
JPS62150588A (ja) * 1985-12-25 1987-07-04 Hitachi Ltd 半導体記憶装置
JPS62192086A (ja) * 1986-02-18 1987-08-22 Matsushita Electronics Corp 半導体記憶装置
JPS6366138A (ja) * 1987-03-18 1988-03-24 Takeda Chem Ind Ltd 10−メチル−9−ドデセン−1−オ−ル類及びその製造法

Also Published As

Publication number Publication date
JP2000100167A (ja) 2000-04-07
KR0143237B1 (ko) 1998-08-17
EP0632461A3 (de) 1995-02-15
DE68928589D1 (de) 1998-04-02
DE68927248D1 (de) 1996-10-31
JP3020966B2 (ja) 2000-03-15
EP0365876B1 (de) 1996-09-25
EP0632461B1 (de) 1998-02-25
EP0365876A2 (de) 1990-05-02
DE68927248T2 (de) 1997-02-06
EP0632461A2 (de) 1995-01-04
HK1017577A1 (en) 1999-11-19
JPH02177080A (ja) 1990-07-10
EP0365876A3 (de) 1991-10-02
KR900006859A (ko) 1990-05-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee