DE68928589T2 - Storage arrangement - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to a memory device as defined in the preamble of claim 1.

DE-A-3 447 722 discloses a memory device of this type which uses a distributed decoder.

BACKGROUND OF THE INVENTION

Industrial users of dynamic random access memory (DRAM) are demanding ever faster timing and ever lower power specifications. To meet these specifications, designers must design DRAMs to read from and write to DRAM memory cells ever faster while using less power. This requires discovering improved methods for driving DRAM word lines to Vdd during the precharge portion of the read cycle and for booting these DRAM word lines to more than Vdd during the active restore portion of the cycle. These functions are a significant part of the length of an active cycle.

A selected row line is driven for reading and booted for the active recovery function using a drive/boot signal sent from a drive/boot signal generator, which is usually located in a peripheral area of the chip. Increasing importance is attached to the decoding path of this drive/boot signal from the drive/boot signal generator to the active word lines. If this decoding path is too resistive or capacitive, the drive and boot of the word lines takes place too slow. In addition, if the drive/boot signal path is too capacitive, the device will consume too much power.

To illustrate the shortcomings of the current drive/boot signal decoding system, two examples are described. In a pair of conventional 64K and 256K DRAM designs, a drive/boot generator is provided. Its output is split into two separate global signal lines (i.e., signal lines that span the entire array) using transfer gates. In any given cycle, therefore, only one of the split lines needs to be active. Then, to drive and boot the correct word lines, each of the split lines is connected to one-half of all the word line drivers or decoders in the DRAM. The row decoders are selected by addressing signals. Therefore, in any given cycle, the one master drive/boot signal "sees" the parasitic capacitance of one-half of all the wordline drivers on the entire chip that are connected to it, plus the parasitic capacitance of two auxiliary decode transfer gates. To reach each decoded wordline, the drive/boot signal must pass through the resistance of a transfer gate and a wordline driver, in addition to the relatively large amount of capacitance this creates.

According to another conventional design used in 256K and 1M CMOS DRAMs, four drive/boot generators are provided with four separate global drive/boot signal lines. During any given cycle, only one of these signal lines is active. Each drive/boot signal line is directly connected to a quarter of all the word line drivers on the chip. The four generators used according to this method require more space on the chip than one large signal generator. Furthermore, each of the four drive/boot signal lines is provided with a quarter of the parasitic The capacity of the word line drivers of the entire chip is heavily loaded. In order to reach each word line, each control/boot signal must continue to run through the resistance of a word line driver.

The above conventional drive/boot signal decoding solutions require the drive/boot signal to "see" an undesirably high amount of parasitic capacitance and therefore slow down cycle times. The importance of minimizing this capacitance increases with increasing cycle speed, smaller voltage differentials and larger array sizes as required for 4 M DRAM. A need has therefore arisen for a drive/boot signal decoding scheme that results in improved parasitic capacitance characteristics.

The problem to be solved by the invention is to provide a decoding system with an improved property of the parasitic capacitance.

SUMMARY OF THE INVENTION

According to the invention, the above-mentioned problem is solved by a memory device having the characterizing features of claim 1. It is based on the creation of local predecoders, i.e. predecoders which are located directly adjacent to the decoder sections.

A major advantage of the invention is the reduction in the number of row line decoders that the main drive/boot signal "sees". In a 4 M DRAM design according to the invention, the main drive/boot signal sees the parasitic capacitance of only 4/128 of the entire chip's word line drivers plus the capacitance of an additional 128 predecode transfer gates. However, in order to make the rise time of the word lines approximately the same as the rise time using the earlier 256 K and 1 M CMOS techniques, each of the additional 128 predecode transfer gates are approximately four times larger than any word line driver. It is therefore estimated that the parasitic capacitance on the drive/boot line in a given cycle according to the invention is approximately only one tenth of the parasitic capacitance of the word line drivers of the entire chip. This allows the word lines to be driven faster while consuming less power.

BRIEF DESCRIPTION OF THE DRAWING

Further aspects of the invention and its advantages will become clear from the following detailed description in conjunction with the drawings in which:

Figure 1 is a partial schematic diagram showing a four megabit DRAM design according to the invention;

Fig. 2 is a simplified schematic layout of a small portion of the DRAM shown in Fig. 1;

Fig. 3 is a detailed circuit diagram of a single predecoder according to the invention; and

Fig. 4 is a detailed circuit diagram of a single decoder according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

First, a design of a dynamic random access memory (DRAM) chip is shown generally at 10 in Figure 1. The particular design shown is for a four megabit DRAM. Chip 10 includes a cell array region generally designated 12 and a pair of end peripheral regions 14 and 16 adjacent to cell array region 12.

In the embodiment shown, a row factor signal generator 18 (RF) and a drive/boot signal generator 20 (RLXH) are formed in the peripheral region 14. The size and positioning of the signal generators 18 and 20 are shown only schematically. The drive/boot signal generator 20 has an output connected to a drive/boot signal generator line 22 which runs down the center of the matrix region 12. The row factor signal generator 18 has a plurality of row factor signal lines 24 (shown schematically; in an actual embodiment there are twenty such lines 24) which also run down the center of the matrix region 12 in such a way that they are substantially parallel to the drive/boot signal line 22.

The array region 12 contains a plurality of DRAM memory cell arrays 26 arranged in rows and columns. In the embodiment shown, thirty-two arrays 26 are arranged in sixteen rows and two columns, each array having 128K memory cells. Only the first five and last four rows are shown, the remaining seven center rows, similar in design, are shown by dashed continuation lines. The arrays 26 are separated from one another in a vertical or column direction by one of a plurality of sense amplifiers 28, and in a row or horizontal direction by a vertical spacing generally designated 30.

The vertical space 30 is partially occupied by a plurality of row decoder sections 32. The design of the arrays 26, sense amplifiers 28 and row decoder sections 32 leaves a plurality of "holes" 34 which are used to locate the predecoders and row redundancy decoders described below. The drive/boot signal line 22 and the row factor signal lines 24 are conveniently routed down the chip within the vertical space 30.

In Fig. 2 a small detail of the design shown in Fig. 1 is shown. The areas provided for the arrangement of the cell arrays 26, the sense amplifiers 28, the decoder sections 32 and the predecoders and the row redundancy decoders described below are indicated by dashed lines. The row decoder sections 32 are preferably arranged in pairs back to back and extend the vertical distance 30 from one cell array 26a in the right column to the opposite cell array 26b in the left column. The embodiment shown contains thirty-two row decoders in each row decoder section 32, with one such row decoder being designated 36 and surrounded by a dashed enclosure. Each row decoder 36 is operable to decode the drive/boot signal line on two of eight word lines, with four word lines located in cell array 26a and the other four word lines located in cell array 26b. Two of these word lines are shown at 38a, 38b.

A predecoder 40 is preferably arranged so that it is adjacent to a respective decoder section 32. The predecoders 40 are arranged so that they use at least a portion of the space created by the "holes" 34. Further, each decoder section 32 is provided with a row redundancy decoder 42, which is preferably arranged in an area adjacent to a respective predecoder 40.

To minimize resistance, the drive/boot signal generator line (RLXH generator line) 22 is formed by a relatively wide strip of conductor made of the second metal and preferably runs down the middle of the vertical pitch 30. As shown schematically by the connection points on the line 22, the line 22 is connected to each row redundancy decoder 42 and each predecoder 40 along the length of the chip.

The row factor (RF) signal lines 24 are generally routed in parallel with the RLXH signal line 22. Each of the twenty row factor signal lines 24 is connected to each row redundancy decoder 42, but only selected row factor signal lines 24 are connected to any one of the predecoder 40 and any one of the decoder 36. The row factor signal lines 24 are connected to a particular predecoder 40 or to a particular decoder 36 according to a decoding scheme described in more detail in connection with FIGS. 3 and 4.

A plurality of predecoder lines 44 extend from the interior of the predecoder 40 and are arranged generally parallel to the row factor signal lines 24. The predecoder lines 44 are preferably formed in the second metal where they are parallel to the row factor lines 24 and (not shown in this schematic) in the first metal where they are parallel to them. In a respective decoder section 32, each predecoder line 44 intersects and is connected to each decoder 36. In the embodiment shown, there are four predecoder output lines 44 and the signals carried on them are named RDD0, RDD1, RDD2 and RDD3 (see Figure 3).

In the embodiment shown, each row redundancy decoder 42 is operable to decode the drive/boot signal onto two selected ones of the four redundant row lines 46. To replace up to two pairs of regular row lines 38 as required, four redundant row lines 46 are provided. The row redundancy scheme referred to here is described in more detail in the co-pending application Ser. No. (Attorney Docket No.: 12989).

A detailed circuit diagram of one of the predecoders 40 is shown in Fig. 3. Several selected row factor lines 24 are connected as inputs to the predecoder circuit 40 and their identity changes according to a predetermined decoding scheme. The row factor lines RF0-RF3 are connected to respective inputs of four NAND gates 50-56. The row factor signal lines RF0-RF3 are connected to each predecoder circuit 40 on the chip. On the other hand, the identity of three other row factor signal input lines RFI, RFJ and RFK changes according to the particular predecoder circuit 40 to which they are connected. The table below provides the identity of RFI, RFJ and RFK according to the cardinal number of the respective predecoder 40. TABLE I

Therefore, seven row factor signal lines connect to the inputs of each predecoder 40, while the remaining thirteen do not.

A predecoder signal output precharge signal RDPC is connected to a gate 58 of a P-channel transistor 60. The current path of transistor 60 selectively connects a voltage source (Vdd) to a node 62. The current path of another P-channel transistor 64 may also be operated to connect Vdd to node 62.

The drain of an N-channel transistor 66 is connected to node 62, while one of its sources is connected to the drain of another N-channel transistor 68. The source of N-channel transistor 68 is connected to a node 70, which in turn is connected to the drains of two N-channel transistors 72 and 74. The sources of N-channel transistors 72 and 74 are connected to ground or Vss. Row factor signal line RFK is connected to the gate of transistor 68. The gate of transistor 72 is connected to signal line RFI, while the gate of transistor 74 is connected to signal line RFJ. The gate of transistor 66 is connected to a row redundancy enable signal line RREN.

Node 62 serves as the input to an inverter 76. The output of inverter 76 is connected to a node 78, which in turn is connected back to the gate of P-channel transistor 64. Node 78 is also connected to two inputs of NAND gates 50-56.

The outputs of NAND gates 50-56 are connected to nodes 80, 82, 84, and 86, respectively. Each node 80-86 is connected to an input of a respective inverter 88-94. The output of each inverter 88-94 is connected to the source of a respective large transfer gate transistor 96-102. A gate of each transfer gate transistor 96-102 is connected to Vdd.

The source of each transfer gate transistor 96, 98, 100 and 102 is connected to the gate of a respective N-channel transistor 104, 106, 108 or 110. The sources of each of the transistors 104-110 are connected to the drive/boot signal line 22 (RLXH). The drains of the transistors 104-110 are connected to respective nodes 112, 114, 116 and 118. Each node 112-118 is connected to the source of a respective ground transistor 120, 122, 124 or 126. The drains of the ground transistors 120-126 are connected to ground or to Vss The gates of each transistor 120-126 are connected back to respective nodes 80-86 through respective lines 128-134. Each node 112-118 is connected to a respective predecoder output line RDD0-RDD3.

Turning now to Fig. 4, a detailed circuit diagram of a decoder circuit 36 is shown. The decoder circuit 36 is enabled by high states of three row factor signals appearing at the respective gates of enable transistors 142, 144 and 146 in the center of Fig. 3. The RF line 24 connected to the gate of transistor 142 is selected from one of lines RF4 through RF7. Similarly, the RF signal line connected to the gate of transistor 144 is selected from RF8 through RF11, and the row factor signal line 24 connected to the gate of transistor 146 is selected from RF12 through RF15. The selection of which of these lines is connected to a particular decoder circuit 36 varies according to the identity of the particular decoder circuit 36 within the decoder section 32 (Fig. 2). In this way, within any decoder section 32, one of the thirty-two decoders can be selected.

A row decoder precharge signal line RDPC is connected to the gate of a P-channel transistor 148. The current path of transistor 148 connects a voltage supply Vdd to a node 150. Node 150 is connected to the inputs of the left and right inverters 152 and 154. The output of inverter 154 is connected to a node 156, which in turn is connected back to the gate of a P-channel transistor 158. The current path of transistor 158 connects a voltage supply Vdd to node 150. Node 150 is connected to a node 164 by lines 160 and 162 and is further connected to a node 168 by lines 160 and 166. Node 150 is selectively connected to Vss or to ground through the current paths of selection transistors 142, 144 and 146.

The output node 156 of the right inverter is connected to the sources of each of four transfer transistors 170, 172, 174 and 176. The drains of transistors 170-176 are in turn connected to lines 178, 180, 182 and 184, respectively. Lines 178-184 are in turn connected to the gates of self-booting decode transistors 186, 188, 190 and 192, respectively.

Node 164 is connected to the gate of each of four row line ground transistors 194, 196, 198 and 200. Ground transistors 194-200 are operable to connect respective word line nodes 202, 204, 206 and 208 to ground. Each row line node 202-208 is connected to a respective row line ROWL0R, ROWL1R, ROWL2R or ROWL3R of the right matrix.

The decoding circuitry for the left matrix is similar to that for the right matrix. An output node 210 of the left inverter 152 is connected to the source of each of a plurality of transfer gate transistors 212, 214, 216 and 218. The drain of each of the transfer gate transistors 212-218 is connected to a gate of a respective self-booting decoding transistor 220, 222, 224 or 226. The current path of each decoding transistor 220-226 connects a respective predecoder output line RDD0-RDD3 to a respective row line node 228, 230, 232 or 234 of the left matrix. The row lines ROWL0L, ROWL1L, ROWL2L and ROWL3L of the left matrix are connected to the respective row line nodes 28-234 of the left matrix.

Decoding a drive/boot signal onto selected left and right row lines is done as follows. Referring again to Fig. 1, a plurality of row factor signals are generated by the row factor signal generator 18 in the peripheral region 14. These run through selected row factor lines 24 to each decoder and predecoder on the chip 10. High Row factor signal states are generated on one of lines RF0-RF3, on one of lines RF4-RF7, on one of lines RF8-RF11, on one of lines RF12-RF15, and on one of lines RF16-19. Now, as shown in Figure 3 and in Table I above, either the RFI or the RFJ of certain selected predecoder circuits 40 are turned on so that either the gate of transistor 72 or the gate of transistor 74 is turned on.

Referring temporarily to Fig. 1, the architecture of the DRAM shown is divided into four quadrants and the decoding scheme operates by selecting one predecoder for each quadrant from the eight predecoders in the quadrant. A DRAM according to the invention could also be divided into halves, octants or any other parts containing an integer quotient of the total number of predecoders.

In Fig. 3, this means that for the selected predecoders, RFK and one RFI or RFJ are in the high state, while the remaining seven of the eight predecoders in the quadrant do not have this enabling combination. To prevent disabling the entire predecoder, signal RREN must also be high. Finally, precharge signal RDPC must go high to turn off P-channel transistor 58 so that node 62 can be pulled low. In each of the selected predecoders 40, the low state of node 62 is inverted to a high state on node 78, which in turn enables each of the NAND gates 50-56. Only one of the row factor signals RF0-RF3 is high, while the rest are low. A selected one of the NAND gate output nodes 80-86, e.g., node 82, is therefore low. The low state on node 82 is inverted by inverter 90 to a high state on the drain of transistor 98. Transistor 98 can be operated to maintain this high state minus a drop Vt to the gate of the respective decoding transistor 106.

Referring briefly to Fig. 1, a drive signal RLXH is sent on the drive/boot signal line 22 from the peripheral region 14 down into the cell array region 12. Returning to Fig. 3, the decode transistor 106, which is turned on (in this example), boots its gate itself to more than Vdd + Vt' while both node RLXH and node 114 rise, allowing a full Vdd to appear on node 114, which in turn is output to the predecoder output line RDD1.

Now in Fig. 4, RDD1 appears at the drain of both the left decode transistor 222 and the right decode transistor 188. For the RF signals sent down the chip from the RF signal generator 18 (Fig. 1), one of thirty-two decoders 36 is selected in each decoding section 32 on the chip. The combination of selecting one of eight predecoders 40 in each quadrant, one RDD line of four RDD lines per predecoder 40, and one decoder 36 of thirty-two decoders 36 (Fig. 2) per predecoder 40 means that only two row lines are active per quadrant. In addition, since the parasitic capacitance of the remaining one hundred ninety-two decode transistors of the thirty-two decoders 36 is covered by the unselected portions of the selected predecoders 40, in other words, the three inactive RDD lines, the RLXH drive/boot signal sees the parasitic capacitance of only sixty-four decode transistors of the thirty-two decoders 36 per quadrant. The entire parasitic capacitance of the other decode transistors in the quadrant is covered by the unselected predecoders 40 in the quadrant before the RLXH drive/boot signal.

A low state on decoder select node 150 in a selected decoder 36 (Fig. 4) is inverted by inverters 152 and 154 and therefore appears as a high state on nodes 156 and 210. To actuate the gates of right decode transistors 186-192 and left decode transistors 220-226, the high states on nodes 156 and 210 are passed through transistors 170, 172, 174, 176, 212, 214, 216 and 218. However, since the gates of transistors 186-192 and 220-226 are charged to Vdd - Vt, this causes Vt to drop across transistors 170-176 and 212-218. The high state of inverter output node 156 also turns off precharge transistor 158. Precharge transistor 148 is turned off by a high state of RDPC.

In the case of the unselected decoders 36, the state of node 150 is high. This high state is communicated to the gates of each of the right and left row line discharge transistors 194, 196, 198, 200, 240, 242, 244 and 246 through lines 160, 162 and 166. The right row line nodes 202-208 and the left row line nodes 228-234 therefore remain discharged.

However, assuming node 150 is high, each of the current paths of transistors 186-192 and 220-226 is actuated to send a high state appearing on any of the predecoder output lines RDD0-RDD3 to an appropriate set of right and left row lines. Carrying out the example that RDD1 is high and that RDD0, RDD2 and RDD3 are low, the high signal RDD1 is sent through the current path of transistors 188 and 222 to respective left and right row line nodes 230 and 204 which bootstrap the gates of transistors 188 and 222 to at least Vdd + Vt' and do not allow any Vt to drop through transistors 188 and 222. The transmission lines ROWL1R and ROWL1L are thereby driven by the drive signal RLXH. The same by decoding the predecoder circuit 40 (Fig. 3) and the decoder circuit 36 (Fig. 4) is used for the boot signal subsequently sent by the drive/boot generator to ROWL1R and ROWL1L during an active recovery portion of the DRAM cycle.

In summary, a two-stage decoding scheme is disclosed that prevents the drive/boot signal from "seeing" the parasitic capacitance of all but a few decoding circuits. Since the predecoder circuits are located locally on the chip, a global drive/boot signal line can be used without excessive power dissipation.

While the above detailed description has shown a practical embodiment and its advantages, the invention is not limited thereby, but only by the scope of the appended claims.

Claims (1)

1. Storage device, with: a plurality of matrices (26) of memory cells within the matrix area (12) of the memory device, the matrices (26) being formed from a plurality of parallel rows and columns; a plurality of decoder sections (32), each of which contains a plurality of decoders (36), each matrix (26) being separated from a next adjacent matrix (26) in the row direction by at least one of the decoder sections (32); a plurality of predecoders (40) formed in the matrix area (12) and connected to the decoder sections, characterized in that between each pair of matrices in the row direction four of the decoder sections (32) are arranged in a 2 × 2 matrix and that each matrix of decoder sections (32) is separated from the next adjacent matrix of decoder sections (32) in a column direction by at least one of the predecoder sections (40).