DE68915608D1 - Speicherarchitektur. - Google Patents

Speicherarchitektur.

Info

Publication number
DE68915608D1
DE68915608D1 DE68915608T DE68915608T DE68915608D1 DE 68915608 D1 DE68915608 D1 DE 68915608D1 DE 68915608 T DE68915608 T DE 68915608T DE 68915608 T DE68915608 T DE 68915608T DE 68915608 D1 DE68915608 D1 DE 68915608D1
Authority
DE
Germany
Prior art keywords
storage architecture
architecture
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68915608T
Other languages
English (en)
Other versions
DE68915608T2 (de
Inventor
Barbara Alane Chappell
Yeong-Chang Lien
Jeffrey Yuh-Fong Tang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE68915608D1 publication Critical patent/DE68915608D1/de
Application granted granted Critical
Publication of DE68915608T2 publication Critical patent/DE68915608T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE68915608T 1988-04-27 1989-03-08 Speicherarchitektur. Expired - Fee Related DE68915608T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/186,546 US4845669A (en) 1988-04-27 1988-04-27 Transporsable memory architecture

Publications (2)

Publication Number Publication Date
DE68915608D1 true DE68915608D1 (de) 1994-07-07
DE68915608T2 DE68915608T2 (de) 1994-12-01

Family

ID=22685368

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68915608T Expired - Fee Related DE68915608T2 (de) 1988-04-27 1989-03-08 Speicherarchitektur.

Country Status (7)

Country Link
US (1) US4845669A (de)
EP (1) EP0339219B1 (de)
JP (1) JPH0215493A (de)
KR (1) KR920009666B1 (de)
BR (1) BR8901970A (de)
CA (1) CA1313421C (de)
DE (1) DE68915608T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2022586C (en) * 1989-08-02 1994-10-11 Teruo Ishihara Scan converter control circuit having memories and address generator for generating zigzag address signal supplied to the memories
US5070480A (en) * 1990-01-08 1991-12-03 Caywood John M Nonvolatile associative memory system
US5177704A (en) * 1990-02-26 1993-01-05 Eastman Kodak Company Matrix transpose memory device
JPH05151778A (ja) * 1991-06-05 1993-06-18 Mitsubishi Electric Corp スタテイツクランダムアクセスメモリおよびその制御方法
JPH0853182A (ja) * 1994-08-08 1996-02-27 Iri Design:Kk Ｃｄメディア収納容器
US7157314B2 (en) 1998-11-16 2007-01-02 Sandisk Corporation Vertically stacked field programmable nonvolatile memory and method of fabrication
US8575719B2 (en) 2000-04-28 2013-11-05 Sandisk 3D Llc Silicon nitride antifuse for use in diode-antifuse memory arrays
US9251899B2 (en) * 2008-02-12 2016-02-02 Virident Systems, Inc. Methods for upgrading main memory in computer systems to two-dimensional memory modules and master memory controllers
US9268746B2 (en) * 2008-03-07 2016-02-23 St Ericsson Sa Architecture for vector memory array transposition using a block transposition accelerator
US20110051485A1 (en) * 2009-08-28 2011-03-03 International Business Machines Corporation Content addressable memory array writing
JP5859605B2 (ja) * 2014-06-17 2016-02-10 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ 並列多次元ワードアドレス可能メモリアーキテクチャ
US10762957B2 (en) 2016-06-30 2020-09-01 University of Pittsburgh—of the Commonwealth System of Higher Education Two-dimensionally accessible non-volatile memory

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3643236A (en) * 1969-12-19 1972-02-15 Ibm Storage having a plurality of simultaneously accessible locations
US3800289A (en) * 1972-05-15 1974-03-26 Goodyear Aerospace Corp Multi-dimensional access solid state memory
JPS5664599U (de) * 1979-10-18 1981-05-30
JPS6055919B2 (ja) * 1980-03-18 1985-12-07 日本電気株式会社 半導体記憶装置
JPS5760586A (en) * 1980-09-26 1982-04-12 Matsushita Electric Ind Co Ltd Random access memory
JPS5771574A (en) * 1980-10-21 1982-05-04 Nec Corp Siemconductor memory circuit
JPS60205895A (ja) * 1984-03-30 1985-10-17 Fujitsu Ltd 半導体記憶装置
JPS61243545A (ja) * 1985-04-22 1986-10-29 Nippon Telegr & Teleph Corp <Ntt> 多方向読み出し１方向書き込みメモリ装置

Also Published As

Publication number Publication date
KR890016568A (ko) 1989-11-29
JPH0215493A (ja) 1990-01-19
CA1313421C (en) 1993-02-02
KR920009666B1 (ko) 1992-10-22
JPH0529992B2 (de) 1993-05-06
EP0339219B1 (de) 1994-06-01
BR8901970A (pt) 1989-12-05
US4845669A (en) 1989-07-04
EP0339219A3 (de) 1991-09-04
DE68915608T2 (de) 1994-12-01
EP0339219A2 (de) 1989-11-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee