DE3484142D1 - Dynamische halbleiterspeicheranordnung. - Google Patents

Dynamische halbleiterspeicheranordnung.

Info

Publication number
DE3484142D1
DE3484142D1 DE8484102612T DE3484142T DE3484142D1 DE 3484142 D1 DE3484142 D1 DE 3484142D1 DE 8484102612 T DE8484102612 T DE 8484102612T DE 3484142 T DE3484142 T DE 3484142T DE 3484142 D1 DE3484142 D1 DE 3484142D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
dynamic semiconductor
dynamic
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484102612T
Other languages
English (en)
Inventor
Tohru Furuyama
Yukimasa Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3484142D1 publication Critical patent/DE3484142D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
DE8484102612T 1983-03-10 1984-03-09 Dynamische halbleiterspeicheranordnung. Expired - Lifetime DE3484142D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58039550A JPS59165449A (ja) 1983-03-10 1983-03-10 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3484142D1 true DE3484142D1 (de) 1991-04-04

Family

ID=12556162

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484102612T Expired - Lifetime DE3484142D1 (de) 1983-03-10 1984-03-09 Dynamische halbleiterspeicheranordnung.

Country Status (4)

Country Link
US (1) US4697252A (de)
EP (1) EP0121798B1 (de)
JP (1) JPS59165449A (de)
DE (1) DE3484142D1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61280651A (ja) * 1985-05-24 1986-12-11 Fujitsu Ltd 半導体記憶装置
US5051959A (en) * 1985-08-14 1991-09-24 Fujitsu Limited Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type
US4760560A (en) * 1985-08-30 1988-07-26 Kabushiki Kaisha Toshiba Random access memory with resistance to crystal lattice memory errors
JPH0289357A (ja) * 1988-09-27 1990-03-29 Nec Corp 半導体回路
GB9007791D0 (en) * 1990-04-06 1990-06-06 Foss Richard C High voltage boosted wordline supply charge pump and regulator for dram
US5267201A (en) * 1990-04-06 1993-11-30 Mosaid, Inc. High voltage boosted word line supply charge pump regulator for DRAM
GB9007790D0 (en) 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
JP3107556B2 (ja) * 1990-06-01 2000-11-13 株式会社東芝 ダイナミック型半導体記憶装置
KR100198659B1 (ko) 1996-05-16 1999-06-15 구본준 메모리 셀, 메모리 장치 및 그의 제조 방법
US5253202A (en) * 1991-02-05 1993-10-12 International Business Machines Corporation Word line driver circuit for dynamic random access memories
JPH056675A (ja) * 1991-06-27 1993-01-14 Nec Corp スタテイツク型半導体メモリ装置
JP3093432B2 (ja) * 1992-04-08 2000-10-03 日本電気株式会社 行デコーダ
US5600598A (en) * 1994-12-14 1997-02-04 Mosaid Technologies Incorporated Memory cell and wordline driver for embedded DRAM in ASIC process
US7798471B2 (en) * 2006-08-15 2010-09-21 Hydralift Amclyde, Inc. Direct acting single sheave active/passive heave compensator

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3938109A (en) * 1975-02-19 1976-02-10 Intel Corporation High speed ECL compatible MOS-Ram
GB1521955A (en) * 1976-03-16 1978-08-23 Tokyo Shibaura Electric Co Semiconductor memory device
US4364075A (en) * 1980-09-02 1982-12-14 Intel Corporation CMOS Dynamic RAM cell and method of fabrication
US4511811A (en) * 1982-02-08 1985-04-16 Seeq Technology, Inc. Charge pump for providing programming voltage to the word lines in a semiconductor memory array

Also Published As

Publication number Publication date
EP0121798B1 (de) 1991-02-27
EP0121798A3 (en) 1988-03-23
EP0121798A2 (de) 1984-10-17
JPS6146977B2 (de) 1986-10-16
US4697252A (en) 1987-09-29
JPS59165449A (ja) 1984-09-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee