DE3382163D1 - Halbleiterspeicheranordnung mit dekodiermitteln. - Google Patents

Halbleiterspeicheranordnung mit dekodiermitteln.

Info

Publication number
DE3382163D1
DE3382163D1 DE8383307901T DE3382163T DE3382163D1 DE 3382163 D1 DE3382163 D1 DE 3382163D1 DE 8383307901 T DE8383307901 T DE 8383307901T DE 3382163 T DE3382163 T DE 3382163T DE 3382163 D1 DE3382163 D1 DE 3382163D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
decoding
agents
decoding agents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8383307901T
Other languages
English (en)
Inventor
Yasuro Matsuzaki
Toshitaka Fukushima
Kouji Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3382163D1 publication Critical patent/DE3382163D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
DE8383307901T 1982-12-29 1983-12-22 Halbleiterspeicheranordnung mit dekodiermitteln. Expired - Fee Related DE3382163D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57233906A JPS59124092A (ja) 1982-12-29 1982-12-29 メモリ装置

Publications (1)

Publication Number Publication Date
DE3382163D1 true DE3382163D1 (de) 1991-03-28

Family

ID=16962433

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383307901T Expired - Fee Related DE3382163D1 (de) 1982-12-29 1983-12-22 Halbleiterspeicheranordnung mit dekodiermitteln.

Country Status (5)

Country Link
US (1) US4617653A (de)
EP (1) EP0115187B1 (de)
JP (1) JPS59124092A (de)
DE (1) DE3382163D1 (de)
IE (1) IE56715B1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6148192A (ja) * 1984-08-11 1986-03-08 Fujitsu Ltd 半導体記憶装置
JPS6167154A (ja) * 1984-09-11 1986-04-07 Fujitsu Ltd 半導体記憶装置
JPS61199297A (ja) * 1985-02-28 1986-09-03 Toshiba Corp 半導体記憶装置
JPS61265794A (ja) * 1985-05-20 1986-11-25 Fujitsu Ltd 半導体記憶装置のデコ−ダ回路
JP2603205B2 (ja) * 1987-03-16 1997-04-23 シーメンス、アクチエンゲゼルシヤフト 多段集積デコーダ装置
US5257234A (en) * 1987-07-15 1993-10-26 Hitachi, Ltd. Semiconductor integrated circuit device
EP0299697B1 (de) * 1987-07-15 1993-09-29 Hitachi, Ltd. Integrierte Halbleiterschaltungsanordnung
KR920010344B1 (ko) * 1989-12-29 1992-11-27 삼성전자주식회사 반도체 메모리 어레이의 구성방법
KR930001738B1 (ko) * 1989-12-29 1993-03-12 삼성전자주식회사 반도체 메모리장치의 워드라인 드라이버 배치방법
KR930001737B1 (ko) * 1989-12-29 1993-03-12 삼성전자 주식회사 반도체 메모리 어레이의 워드라인 배열방법
US5652723A (en) * 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
EP0596198B1 (de) * 1992-07-10 2000-03-29 Sony Corporation Flash-EPROM mit Löschprüfung und Architektur zum Adresszerhacken
JP2001126475A (ja) * 1999-10-25 2001-05-11 Mitsubishi Electric Corp 半導体記憶装置
US8755213B2 (en) 2012-02-29 2014-06-17 International Business Machines Corporation Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming
US8842491B2 (en) 2012-07-17 2014-09-23 International Business Machines Corporation Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3599182A (en) * 1969-01-15 1971-08-10 Ibm Means for reducing power consumption in a memory device
US3688280A (en) * 1970-09-22 1972-08-29 Ibm Monolithic memory system with bi-level powering for reduced power consumption
US4027285A (en) * 1973-12-26 1977-05-31 Motorola, Inc. Decode circuitry for bipolar random access memory
JPS528739A (en) * 1975-07-10 1977-01-22 Fujitsu Ltd Electronic circuit
JPS5631137A (en) * 1979-08-22 1981-03-28 Fujitsu Ltd Decoder circuit
JPS56112122A (en) * 1980-02-08 1981-09-04 Fujitsu Ltd Decoder circuit
JPS5841597B2 (ja) * 1980-12-24 1983-09-13 富士通株式会社 半導体メモリディスチャ−ジ回路

Also Published As

Publication number Publication date
IE833081L (en) 1984-06-29
EP0115187A2 (de) 1984-08-08
EP0115187B1 (de) 1991-02-20
JPS59124092A (ja) 1984-07-18
US4617653A (en) 1986-10-14
JPH0323995B2 (de) 1991-04-02
EP0115187A3 (en) 1986-12-30
IE56715B1 (en) 1991-11-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee