DE3587457T2 - Halbleiterspeichereinrichtung. - Google Patents

Halbleiterspeichereinrichtung.

Info

Publication number
DE3587457T2
DE3587457T2 DE89121879T DE3587457T DE3587457T2 DE 3587457 T2 DE3587457 T2 DE 3587457T2 DE 89121879 T DE89121879 T DE 89121879T DE 3587457 T DE3587457 T DE 3587457T DE 3587457 T2 DE3587457 T2 DE 3587457T2
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE89121879T
Other languages
English (en)
Other versions
DE3587457D1 (de
Inventor
Sumio Tanaka
Shinji Saito
Shigeru Atsumi
Nobuaki Ohtsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59252313A external-priority patent/JPS61131296A/ja
Priority claimed from JP60224060A external-priority patent/JPS6282598A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3587457D1 publication Critical patent/DE3587457D1/de
Application granted granted Critical
Publication of DE3587457T2 publication Critical patent/DE3587457T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
DE89121879T 1984-11-29 1985-11-29 Halbleiterspeichereinrichtung. Expired - Lifetime DE3587457T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59252313A JPS61131296A (ja) 1984-11-29 1984-11-29 半導体記憶装置
JP60224060A JPS6282598A (ja) 1985-10-08 1985-10-08 半導体メモリ

Publications (2)

Publication Number Publication Date
DE3587457D1 DE3587457D1 (de) 1993-08-19
DE3587457T2 true DE3587457T2 (de) 1993-12-09

Family

ID=26525827

Family Applications (2)

Application Number Title Priority Date Filing Date
DE89121879T Expired - Lifetime DE3587457T2 (de) 1984-11-29 1985-11-29 Halbleiterspeichereinrichtung.
DE8585115143T Expired - Lifetime DE3580454D1 (de) 1984-11-29 1985-11-29 Halbleiterspeicheranordnung.

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE8585115143T Expired - Lifetime DE3580454D1 (de) 1984-11-29 1985-11-29 Halbleiterspeicheranordnung.

Country Status (3)

Country Link
US (1) US4694429A (de)
EP (2) EP0361546B1 (de)
DE (2) DE3587457T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6231094A (ja) * 1985-08-01 1987-02-10 Toshiba Corp 不揮発性半導体記憶装置
EP0257912A3 (de) * 1986-08-29 1989-08-23 Kabushiki Kaisha Toshiba Statische Halbleiterspeicheranordnung
US5707697A (en) 1987-03-27 1998-01-13 Avery Dennison Corporation Dry paint transfer product having high DOI automotive paint coat
EP0301521B1 (de) * 1987-07-29 1992-09-09 Kabushiki Kaisha Toshiba Nichtflüchtiger Halbleiterspeicher
US5237534A (en) * 1989-04-27 1993-08-17 Kabushiki Kaisha Toshiba Data sense circuit for a semiconductor nonvolatile memory device
JPH0814996B2 (ja) * 1989-06-27 1996-02-14 株式会社東芝 半導体記憶装置
JPH03176890A (ja) * 1989-12-04 1991-07-31 Toshiba Corp 複数ポート半導体メモリ
JP2875321B2 (ja) * 1990-01-29 1999-03-31 沖電気工業株式会社 半導体記憶装置
FR2659165A1 (fr) * 1990-03-05 1991-09-06 Sgs Thomson Microelectronics Memoire ultra-rapide comportant un limiteur de la tension de drain des cellules.
JPH0438697A (ja) * 1990-05-31 1992-02-07 Oki Electric Ind Co Ltd 半導体記憶装置のデータバスクランプ回路
US5260904A (en) * 1990-05-31 1993-11-09 Oki Electric Industry Co., Ltd. Data bus clamp circuit for a semiconductor memory device
US5481492A (en) * 1994-12-14 1996-01-02 The United States Of America As Represented By The Secretary Of The Navy Floating gate injection voltage regulator
US5828603A (en) * 1997-04-23 1998-10-27 Atmel Corporation Memory device having a power supply-independent low power consumption bit line voltage clamp
JP2009295221A (ja) * 2008-06-04 2009-12-17 Toshiba Corp 半導体記憶装置
FR3007629B1 (fr) * 2013-06-26 2015-08-07 Oreal Dispositif d'application d'un produit cosmetique

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5341968A (en) * 1976-09-29 1978-04-15 Hitachi Ltd Semiconductor circuit
US4195356A (en) * 1978-11-16 1980-03-25 Electronic Memories And Magnetics Corporation Sense line termination circuit for semiconductor memory systems
US4223394A (en) * 1979-02-13 1980-09-16 Intel Corporation Sensing amplifier for floating gate memory devices
JPS606040B2 (ja) * 1979-06-07 1985-02-15 日本電気株式会社 集積回路
JPS57127989A (en) * 1981-02-02 1982-08-09 Hitachi Ltd Mos static type ram
JPS58137194A (ja) * 1982-02-10 1983-08-15 Hitachi Ltd 半導体記憶装置
US4488263A (en) * 1982-03-29 1984-12-11 Fairchild Camera & Instrument Corp. Bypass circuit for word line cell discharge current

Also Published As

Publication number Publication date
EP0361546A2 (de) 1990-04-04
DE3587457D1 (de) 1993-08-19
EP0184148A2 (de) 1986-06-11
EP0184148B1 (de) 1990-11-07
EP0184148A3 (en) 1987-10-07
EP0361546A3 (en) 1990-08-29
DE3580454D1 (de) 1990-12-13
US4694429A (en) 1987-09-15
EP0361546B1 (de) 1993-07-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)