IT1160028B - Processo di fabbricazione di circuiti integrati - Google Patents

Processo di fabbricazione di circuiti integrati

Info

Publication number
IT1160028B
IT1160028B IT29280/78A IT2928078A IT1160028B IT 1160028 B IT1160028 B IT 1160028B IT 29280/78 A IT29280/78 A IT 29280/78A IT 2928078 A IT2928078 A IT 2928078A IT 1160028 B IT1160028 B IT 1160028B
Authority
IT
Italy
Prior art keywords
manufacturing process
integrated circuits
circuits manufacturing
integrated
manufacturing
Prior art date
Application number
IT29280/78A
Other languages
English (en)
Italian (it)
Other versions
IT7829280A0 (it
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT7829280A0 publication Critical patent/IT7829280A0/it
Application granted granted Critical
Publication of IT1160028B publication Critical patent/IT1160028B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D64/0131—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • H10P95/00—
    • H10W20/066—
    • H10W20/4451—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides
IT29280/78A 1977-11-11 1978-10-31 Processo di fabbricazione di circuiti integrati IT1160028B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/850,586 US4128670A (en) 1977-11-11 1977-11-11 Fabrication method for integrated circuits with polysilicon lines having low sheet resistance

Publications (2)

Publication Number Publication Date
IT7829280A0 IT7829280A0 (it) 1978-10-31
IT1160028B true IT1160028B (it) 1987-03-04

Family

ID=25308566

Family Applications (1)

Application Number Title Priority Date Filing Date
IT29280/78A IT1160028B (it) 1977-11-11 1978-10-31 Processo di fabbricazione di circuiti integrati

Country Status (6)

Country Link
US (1) US4128670A (enExample)
EP (1) EP0002165B1 (enExample)
JP (1) JPS5469972A (enExample)
CA (1) CA1092726A (enExample)
DE (1) DE2861516D1 (enExample)
IT (1) IT1160028B (enExample)

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US4908679A (en) * 1981-01-23 1990-03-13 National Semiconductor Corporation Low resistance Schottky diode on polysilicon/metal-silicide
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DE3250096C2 (de) * 1981-05-27 1997-09-11 Hitachi Ltd Verfahren zur Herstellung einer einen MISFET enthaltenden Halbleiterschaltung
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US4640844A (en) * 1984-03-22 1987-02-03 Siemens Aktiengesellschaft Method for the manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon
JPH067584B2 (ja) * 1984-04-05 1994-01-26 日本電気株式会社 半導体メモリ
FR2578272B1 (fr) * 1985-03-01 1987-05-22 Centre Nat Rech Scient Procede de formation sur un substrat d'une couche de siliciure de tungstene, utilisable notamment pour la realisation de couches d'interconnexion des circuits integres.
JPS60221676A (ja) * 1985-03-18 1985-11-06 株式会社日立製作所 冷蔵庫
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KR970003903B1 (en) * 1987-04-24 1997-03-22 Hitachi Mfg Kk Semiconductor device and fabricating method thereof
KR900008868B1 (ko) * 1987-09-30 1990-12-11 삼성전자 주식회사 저항성 접촉을 갖는 반도체 장치의 제조방법
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US4833099A (en) * 1988-01-07 1989-05-23 Intel Corporation Tungsten-silicide reoxidation process including annealing in pure nitrogen and subsequent oxidation in oxygen
JPH0752774B2 (ja) * 1988-04-25 1995-06-05 日本電気株式会社 半導体装置
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US5483104A (en) * 1990-01-12 1996-01-09 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
JPH0680638B2 (ja) * 1990-07-05 1994-10-12 株式会社東芝 半導体装置の製造方法
DE4021516A1 (de) * 1990-07-06 1992-01-16 Samsung Electronics Co Ltd Verfahren zum differenzierten aufwachsen von wolfram fuer die selektive chemische abscheidung aus der gasphase
US5043690A (en) * 1990-07-12 1991-08-27 Sundstrand Data Control, Inc. Balanced snap action thermal actuator
US5034348A (en) * 1990-08-16 1991-07-23 International Business Machines Corp. Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit
KR920015622A (ko) * 1991-01-31 1992-08-27 원본미기재 집적 회로의 제조방법
US5346836A (en) * 1991-06-06 1994-09-13 Micron Technology, Inc. Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects
JP2889061B2 (ja) * 1992-09-25 1999-05-10 ローム株式会社 半導体記憶装置およびその製法
US6284584B1 (en) 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
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JP3380086B2 (ja) * 1995-05-26 2003-02-24 三菱電機株式会社 半導体装置の製造方法
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Also Published As

Publication number Publication date
EP0002165A1 (fr) 1979-05-30
US4128670A (en) 1978-12-05
EP0002165B1 (fr) 1982-01-06
JPS5469972A (en) 1979-06-05
IT7829280A0 (it) 1978-10-31
CA1092726A (en) 1980-12-30
JPS6128232B2 (enExample) 1986-06-28
DE2861516D1 (en) 1982-02-25

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19951027