FR2761526B1 - Procede pour fabriquer une tranche de silicium et tranche de silicium fabriquee par ce procede - Google Patents

Procede pour fabriquer une tranche de silicium et tranche de silicium fabriquee par ce procede

Info

Publication number
FR2761526B1
FR2761526B1 FR9715079A FR9715079A FR2761526B1 FR 2761526 B1 FR2761526 B1 FR 2761526B1 FR 9715079 A FR9715079 A FR 9715079A FR 9715079 A FR9715079 A FR 9715079A FR 2761526 B1 FR2761526 B1 FR 2761526B1
Authority
FR
France
Prior art keywords
silicon slice
making
manufactured
silicon
slice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR9715079A
Other languages
English (en)
Other versions
FR2761526A1 (fr
Inventor
Hidekazu Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of FR2761526A1 publication Critical patent/FR2761526A1/fr
Application granted granted Critical
Publication of FR2761526B1 publication Critical patent/FR2761526B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
FR9715079A 1997-03-31 1997-12-01 Procede pour fabriquer une tranche de silicium et tranche de silicium fabriquee par ce procede Expired - Lifetime FR2761526B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9080939A JPH10275905A (ja) 1997-03-31 1997-03-31 シリコンウェーハの製造方法およびシリコンウェーハ

Publications (2)

Publication Number Publication Date
FR2761526A1 FR2761526A1 (fr) 1998-10-02
FR2761526B1 true FR2761526B1 (fr) 2002-08-30

Family

ID=13732451

Family Applications (2)

Application Number Title Priority Date Filing Date
FR9715079A Expired - Lifetime FR2761526B1 (fr) 1997-03-31 1997-12-01 Procede pour fabriquer une tranche de silicium et tranche de silicium fabriquee par ce procede
FR9806168A Expired - Fee Related FR2762136B1 (fr) 1997-03-31 1998-05-15 Procede pour fabriquer une tranche de silicium et tranche de silicium fabriquee par ce procede

Family Applications After (1)

Application Number Title Priority Date Filing Date
FR9806168A Expired - Fee Related FR2762136B1 (fr) 1997-03-31 1998-05-15 Procede pour fabriquer une tranche de silicium et tranche de silicium fabriquee par ce procede

Country Status (5)

Country Link
JP (1) JPH10275905A (fr)
KR (1) KR19980079501A (fr)
DE (1) DE19753494A1 (fr)
FR (2) FR2761526B1 (fr)
TW (1) TW409418B (fr)

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US20070122997A1 (en) 1998-02-19 2007-05-31 Silicon Genesis Corporation Controlled process and resulting device
US5985742A (en) 1997-05-12 1999-11-16 Silicon Genesis Corporation Controlled cleavage process and device for patterned films
JP3451908B2 (ja) * 1997-11-05 2003-09-29 信越半導体株式会社 Ｓｏｉウエーハの熱処理方法およびｓｏｉウエーハ
JP2007184626A (ja) * 1997-12-26 2007-07-19 Canon Inc Ｓｏｉ基板の熱処理方法及び作製方法
JPH11307472A (ja) * 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP3635200B2 (ja) * 1998-06-04 2005-04-06 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
FR2787919B1 (fr) * 1998-12-23 2001-03-09 Thomson Csf Procede de realisation d'un substrat destine a faire croitre un compose nitrure
JP2000223683A (ja) * 1999-02-02 2000-08-11 Canon Inc 複合部材及びその分離方法、貼り合わせ基板及びその分離方法、移設層の移設方法、並びにｓｏｉ基板の製造方法
JP2000256094A (ja) * 1999-03-08 2000-09-19 Speedfam-Ipec Co Ltd シリコンエピタキシャル成長ウェーハ製造方法およびその装置
JP3911901B2 (ja) 1999-04-09 2007-05-09 信越半導体株式会社 Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法
US6287941B1 (en) 1999-04-21 2001-09-11 Silicon Genesis Corporation Surface finishing of SOI substrates using an EPI process
JP3900741B2 (ja) * 1999-05-21 2007-04-04 信越半導体株式会社 Ｓｏｉウェーハの製造方法
FR2797713B1 (fr) 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
FR2797714B1 (fr) 1999-08-20 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
US6489241B1 (en) * 1999-09-17 2002-12-03 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film
JP4529036B2 (ja) * 1999-09-24 2010-08-25 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 半導体用薄膜ウェハの製造方法
JP2008028415A (ja) * 1999-10-14 2008-02-07 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
EP2259299A1 (fr) 1999-10-14 2010-12-08 Shin-Etsu Handotai Co., Ltd. Procédé de fabrication de tranche SOI, et tranche SOI
KR100549257B1 (ko) * 1999-12-08 2006-02-03 주식회사 실트론 에스오아이 웨이퍼의 표면 정밀 가공 방법
JP4450126B2 (ja) * 2000-01-21 2010-04-14 日新電機株式会社 シリコン系結晶薄膜の形成方法
KR100800637B1 (ko) * 2000-12-22 2008-02-01 엔엑스피 비 브이 반도체 디바이스
CN100524652C (zh) * 2001-07-05 2009-08-05 东京毅力科创株式会社 基片处理装置及基片处理方法
FR2827423B1 (fr) * 2001-07-16 2005-05-20 Soitec Silicon On Insulator Procede d'amelioration d'etat de surface
KR100434914B1 (ko) * 2001-10-19 2004-06-09 주식회사 실트론 고품질 웨이퍼 및 그의 제조방법
KR100467837B1 (ko) * 2002-05-17 2005-01-24 주식회사 실트론 에스오아이 웨이퍼 제조방법
KR100465527B1 (ko) * 2002-11-21 2005-01-13 주식회사 실트론 Ｓｏｉ 웨이퍼의 결함 제거 및 표면 경면화 방법
RU2217842C1 (ru) * 2003-01-14 2003-11-27 Институт физики полупроводников - Объединенного института физики полупроводников СО РАН Способ изготовления структуры кремний-на-изоляторе
FR2853991B1 (fr) * 2003-04-17 2005-10-28 Soitec Silicon On Insulator Procede de traitement de substrats demontables, et substrat intermediaire demontable, avec polissage perfectionne
DE60336543D1 (de) 2003-05-27 2011-05-12 Soitec Silicon On Insulator Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur
US6911376B2 (en) * 2003-10-01 2005-06-28 Wafermasters Selective heating using flash anneal
US8993410B2 (en) 2006-09-08 2015-03-31 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US8293619B2 (en) 2008-08-28 2012-10-23 Silicon Genesis Corporation Layer transfer of films utilizing controlled propagation
US7811900B2 (en) 2006-09-08 2010-10-12 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
US9362439B2 (en) 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
EP1926130A1 (fr) 2006-11-27 2008-05-28 S.O.I.TEC. Silicon on Insulator Technologies S.A. Procéde d'amélioration de la surface d'un substrat semiconducteur
US7883988B2 (en) * 2008-06-04 2011-02-08 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
US8330126B2 (en) 2008-08-25 2012-12-11 Silicon Genesis Corporation Race track configuration and method for wafering silicon solar substrates
JP5625239B2 (ja) * 2008-12-25 2014-11-19 信越半導体株式会社 貼り合わせウェーハの製造方法
US8329557B2 (en) 2009-05-13 2012-12-11 Silicon Genesis Corporation Techniques for forming thin films by implantation with reduced channeling
JP2011253906A (ja) 2010-06-01 2011-12-15 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4786615A (en) * 1987-08-31 1988-11-22 Motorola Inc. Method for improved surface planarity in selective epitaxial silicon
DD266888A1 (de) * 1987-11-12 1989-04-12 Akad Wissenschaften Ddr Verfahren zur oberflaechenglaettung dicker soi-schichten
JPH04162628A (ja) * 1990-10-26 1992-06-08 Nec Corp 半導体装置の製造方法
TW211621B (fr) * 1991-07-31 1993-08-21 Canon Kk
DE69333619T2 (de) * 1992-01-30 2005-09-29 Canon K.K. Herstellungsverfahren für Halbleitersubstrate
US5427055A (en) * 1992-01-31 1995-06-27 Canon Kabushiki Kaisha Method for controlling roughness on surface of monocrystal
JPH0766376A (ja) * 1993-08-26 1995-03-10 Toshiba Corp 半導体基板の製造方法
JP3293736B2 (ja) * 1996-02-28 2002-06-17 キヤノン株式会社 半導体基板の作製方法および貼り合わせ基体
JP3542376B2 (ja) * 1994-04-08 2004-07-14 キヤノン株式会社 半導体基板の製造方法
SG65697A1 (en) * 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article

Also Published As

Publication number Publication date
FR2762136A1 (fr) 1998-10-16
JPH10275905A (ja) 1998-10-13
KR19980079501A (ko) 1998-11-25
TW409418B (en) 2000-10-21
FR2762136B1 (fr) 2001-11-16
FR2761526A1 (fr) 1998-10-02
DE19753494A1 (de) 1998-10-01

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