FI20041525A0 - Elektroniikka moduuli ja menetelmä sen valmistamiseksi - Google Patents

Elektroniikka moduuli ja menetelmä sen valmistamiseksi

Info

Publication number
FI20041525A0
FI20041525A0 FI20041525A FI20041525A FI20041525A0 FI 20041525 A0 FI20041525 A0 FI 20041525A0 FI 20041525 A FI20041525 A FI 20041525A FI 20041525 A FI20041525 A FI 20041525A FI 20041525 A0 FI20041525 A0 FI 20041525A0
Authority
FI
Finland
Prior art keywords
contact terminals
insulating
material layer
conductor structures
component
Prior art date
Application number
FI20041525A
Other languages
English (en)
Swedish (sv)
Other versions
FI20041525A (fi
Inventor
Risto Tuominen
Antti Iihola
Original Assignee
Imbera Electronics Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imbera Electronics Oy filed Critical Imbera Electronics Oy
Priority to FI20041525A priority Critical patent/FI20041525A/fi
Publication of FI20041525A0 publication Critical patent/FI20041525A0/fi
Priority to JP2007542020A priority patent/JP2008522397A/ja
Priority to PCT/FI2005/000506 priority patent/WO2006056648A2/en
Priority to US11/791,547 priority patent/US8547701B2/en
Publication of FI20041525A publication Critical patent/FI20041525A/fi

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/28—Web or sheet containing structurally defined element or component and having an adhesive outermost layer
    • Y10T428/2804—Next to metal
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PCT/FI2005/000506 WO2006056648A2 (en) 2004-11-26 2005-11-24 Electronics module and method for manufacturing the same
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FI20041525A (fi) 2006-03-17
WO2006056648A3 (en) 2006-08-31
JP2008522397A (ja) 2008-06-26
US20080094805A1 (en) 2008-04-24
US8547701B2 (en) 2013-10-01

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