ES8702677A1 - Disposicion destinada a repartir prioridad a ordenadores quecontienen procesadores de dos tipos - Google Patents

Disposicion destinada a repartir prioridad a ordenadores quecontienen procesadores de dos tipos

Info

Publication number
ES8702677A1
ES8702677A1 ES549805A ES549805A ES8702677A1 ES 8702677 A1 ES8702677 A1 ES 8702677A1 ES 549805 A ES549805 A ES 549805A ES 549805 A ES549805 A ES 549805A ES 8702677 A1 ES8702677 A1 ES 8702677A1
Authority
ES
Spain
Prior art keywords
priority
bus
access
priority unit
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES549805A
Other languages
English (en)
Other versions
ES549805A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of ES549805A0 publication Critical patent/ES549805A0/es
Publication of ES8702677A1 publication Critical patent/ES8702677A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/46—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using electromechanical counter-type accumulators

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Supply And Distribution Of Alternating Current (AREA)
  • Remote Monitoring And Control Of Power-Distribution Networks (AREA)
  • Transmitters (AREA)
  • Electronic Switches (AREA)
  • Steroid Compounds (AREA)
  • Devices For Checking Fares Or Tickets At Control Points (AREA)
  • Saccharide Compounds (AREA)
  • Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
  • Peptides Or Proteins (AREA)
  • Curing Cements, Concrete, And Artificial Stone (AREA)

Abstract

REPARTIDOR DE PRIORIDAD EN ORDENADOR CON PROCESADOR DE DOS TIPOS. CONSTA DE: A) UN PROCESADOR (1) CON ALTA PRIORIDAD, CONECTADO POR LA LINEA GENERAL (2), A UNA PLURALIDAD DE PROCESADORES DE BAJA PRIORIDAD (3A-3H); B) UNA MEMORIA (4) CONECTADA A LA LINEA GENERAL (2), A LA QUE TIENEN ACCESO LOS PROCESADORES A TRAVES DE DICHA LINEA; C) UNA DISPOSICION DE REPARTO DE PRIORIDADES (5), SEPARADA PERO QUE PUEDE ESTAR DIVIDIDA DE MODO QUE ALGUNAS PARTES ESTEN EN LOS PROCESADORES, DONDE BMA F DIRECCION MAESTRA DE LINEA GENERAL; EGB F CESION EXTERNA DE LA LINEA GENERAL; MBG F CESION INTENSIVA DE LA LINEA GENERAL AL PROCESADOR; RQB F ENLACE COMUN SOLICITADO; REB F ENLACE COMUN RESERVADO; Y BOC F ENLACE COMUN OCUPADO.
ES549805A 1984-12-12 1985-12-11 Disposicion destinada a repartir prioridad a ordenadores quecontienen procesadores de dos tipos Expired ES8702677A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE8406312A SE445861B (sv) 1984-12-12 1984-12-12 Prioritetsfordelningsanordning for datorer

Publications (2)

Publication Number Publication Date
ES549805A0 ES549805A0 (es) 1986-12-16
ES8702677A1 true ES8702677A1 (es) 1986-12-16

Family

ID=20358135

Family Applications (1)

Application Number Title Priority Date Filing Date
ES549805A Expired ES8702677A1 (es) 1984-12-12 1985-12-11 Disposicion destinada a repartir prioridad a ordenadores quecontienen procesadores de dos tipos

Country Status (23)

Country Link
US (1) US4791563A (es)
EP (1) EP0205472B1 (es)
JP (1) JPH0630086B2 (es)
KR (1) KR910003015B1 (es)
AT (1) ATE45825T1 (es)
BR (1) BR8507112A (es)
CA (1) CA1241767A (es)
DE (1) DE3572552D1 (es)
DK (1) DK165077C (es)
EG (1) EG17290A (es)
ES (1) ES8702677A1 (es)
FI (1) FI88549C (es)
GR (1) GR852847B (es)
IE (1) IE57050B1 (es)
IT (1) IT1186409B (es)
MA (1) MA20594A1 (es)
MX (1) MX158467A (es)
NO (1) NO170999C (es)
NZ (1) NZ214010A (es)
PT (1) PT81612B (es)
SE (1) SE445861B (es)
TR (1) TR22658A (es)
WO (1) WO1986003606A1 (es)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU595691B2 (en) * 1987-03-26 1990-04-05 Honeywell Bull Inc. Tandem priority resolver
JP2635639B2 (ja) * 1987-12-28 1997-07-30 株式会社東芝 データ処理装置
JP2635995B2 (ja) * 1988-05-18 1997-07-30 株式会社日立製作所 プロセッサを有するシステム
JPH0289149A (ja) * 1988-09-26 1990-03-29 Matsushita Electric Ind Co Ltd バス優先順位装置
US5081578A (en) * 1989-11-03 1992-01-14 Ncr Corporation Arbitration apparatus for a parallel bus
EP0426413B1 (en) * 1989-11-03 1997-05-07 Compaq Computer Corporation Multiprocessor arbitration in single processor arbitration schemes
EP0860780A3 (en) * 1990-03-02 1999-06-30 Fujitsu Limited Bus control system in a multi-processor system
US5414818A (en) * 1990-04-06 1995-05-09 Mti Technology Corporation Method and apparatus for controlling reselection of a bus by overriding a prioritization protocol
US5297277A (en) * 1990-08-31 1994-03-22 International Business Machines Corporation Apparatus for monitoring data transfers of an oemi channel interface
JPH06110825A (ja) * 1992-09-30 1994-04-22 Nec Corp 共通バス制御方式
US5519838A (en) * 1994-02-24 1996-05-21 Hewlett-Packard Company Fast pipelined distributed arbitration scheme
US5740383A (en) * 1995-12-22 1998-04-14 Cirrus Logic, Inc. Dynamic arbitration priority
US6374319B1 (en) 1999-06-22 2002-04-16 Philips Electronics North America Corporation Flag-controlled arbitration of requesting agents
FR2894696A1 (fr) 2005-12-14 2007-06-15 Thomson Licensing Sas Procede d'acces a un bus de transmission de donnees, dispositif et systeme correspondant

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812611B2 (ja) * 1975-10-15 1983-03-09 株式会社東芝 デ−タテンソウセイギヨホウシキ
US4059851A (en) * 1976-07-12 1977-11-22 Ncr Corporation Priority network for devices coupled by a common bus
US4096571A (en) * 1976-09-08 1978-06-20 Codex Corporation System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking
US4096569A (en) * 1976-12-27 1978-06-20 Honeywell Information Systems Inc. Data processing system having distributed priority network with logic for deactivating information transfer requests
SE414087B (sv) * 1977-02-28 1980-07-07 Ellemtel Utvecklings Ab Anordning i ett datorsystem vid utsendning av signaler fran en processor till en eller flera andra processorer varvid prioriterade signaler sends direkt utan tidsfordrojning och oprioriterade signalers ordningsfoljd ...
US4121285A (en) * 1977-04-01 1978-10-17 Ultronic Systems Corporation Automatic alternator for priority circuit
US4257095A (en) * 1978-06-30 1981-03-17 Intel Corporation System bus arbitration, circuitry and methodology
IT1100916B (it) * 1978-11-06 1985-09-28 Honeywell Inf Systems Apparato per gestione di richieste di trasferimento dati in sistemi di elaborazione dati
US4271467A (en) * 1979-01-02 1981-06-02 Honeywell Information Systems Inc. I/O Priority resolver

Also Published As

Publication number Publication date
KR910003015B1 (ko) 1991-05-15
ES549805A0 (es) 1986-12-16
SE8406312L (sv) 1986-06-13
KR870700156A (ko) 1987-03-14
DK381686A (da) 1986-08-11
EG17290A (en) 1989-06-30
FI88549B (fi) 1993-02-15
DK165077B (da) 1992-10-05
ATE45825T1 (de) 1989-09-15
MX158467A (es) 1989-02-03
IT1186409B (it) 1987-11-26
DE3572552D1 (en) 1989-09-28
CA1241767A (en) 1988-09-06
SE445861B (sv) 1986-07-21
DK165077C (da) 1993-02-22
MA20594A1 (fr) 1986-07-01
GR852847B (es) 1985-12-02
SE8406312D0 (sv) 1984-12-12
IT8523124A0 (it) 1985-12-06
EP0205472B1 (en) 1989-08-23
NO862764L (no) 1986-07-08
PT81612A (en) 1986-01-02
BR8507112A (pt) 1987-03-31
JPS62501039A (ja) 1987-04-23
EP0205472A1 (en) 1986-12-30
IE57050B1 (en) 1992-04-08
DK381686D0 (da) 1986-08-11
NZ214010A (en) 1988-10-28
FI862682A0 (fi) 1986-06-24
NO862764D0 (no) 1986-07-08
JPH0630086B2 (ja) 1994-04-20
TR22658A (tr) 1988-02-08
IE853053L (en) 1986-06-12
NO170999B (no) 1992-09-28
FI862682A (fi) 1986-06-24
PT81612B (pt) 1987-09-30
NO170999C (no) 1993-01-06
WO1986003606A1 (en) 1986-06-19
US4791563A (en) 1988-12-13
FI88549C (sv) 1993-05-25

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20061002