KR960009661B1 - Bus arbiter of multi-processor system - Google Patents

Bus arbiter of multi-processor system Download PDF

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Publication number
KR960009661B1
KR960009661B1 KR94007342A KR19940007342A KR960009661B1 KR 960009661 B1 KR960009661 B1 KR 960009661B1 KR 94007342 A KR94007342 A KR 94007342A KR 19940007342 A KR19940007342 A KR 19940007342A KR 960009661 B1 KR960009661 B1 KR 960009661B1
Authority
KR
South Korea
Prior art keywords
processor system
bus arbiter
bus
processors
toggling
Prior art date
Application number
KR94007342A
Other languages
Korean (ko)
Other versions
KR950029956A (en
Inventor
Sung-Mook Lim
Original Assignee
Lg Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Electronics Inc filed Critical Lg Electronics Inc
Priority to KR94007342A priority Critical patent/KR960009661B1/en
Publication of KR950029956A publication Critical patent/KR950029956A/en
Application granted granted Critical
Publication of KR960009661B1 publication Critical patent/KR960009661B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/376—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a contention resolving method, e.g. collision detection, collision avoidance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Abstract

The apparatus includes a flip flop for toggling a bus using signals of 1st and 2nd arbitrating units(20,25) which output oppositely to use a bus alternatively when 1st and 2nd processors(10,15) are accessing to it. The apparatus removes conflicting between processors and provides effective use of buses.
KR94007342A 1994-04-08 1994-04-08 Bus arbiter of multi-processor system KR960009661B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR94007342A KR960009661B1 (en) 1994-04-08 1994-04-08 Bus arbiter of multi-processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR94007342A KR960009661B1 (en) 1994-04-08 1994-04-08 Bus arbiter of multi-processor system

Publications (2)

Publication Number Publication Date
KR950029956A KR950029956A (en) 1995-11-24
KR960009661B1 true KR960009661B1 (en) 1996-07-23

Family

ID=19380635

Family Applications (1)

Application Number Title Priority Date Filing Date
KR94007342A KR960009661B1 (en) 1994-04-08 1994-04-08 Bus arbiter of multi-processor system

Country Status (1)

Country Link
KR (1) KR960009661B1 (en)

Also Published As

Publication number Publication date
KR950029956A (en) 1995-11-24

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