JPS56145448A - Common-use control system - Google Patents

Common-use control system

Info

Publication number
JPS56145448A
JPS56145448A JP4754980A JP4754980A JPS56145448A JP S56145448 A JPS56145448 A JP S56145448A JP 4754980 A JP4754980 A JP 4754980A JP 4754980 A JP4754980 A JP 4754980A JP S56145448 A JPS56145448 A JP S56145448A
Authority
JP
Japan
Prior art keywords
couplers
cpus
cpu
buses
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4754980A
Other languages
Japanese (ja)
Other versions
JPS5836382B2 (en
Inventor
Yasuo Shimizu
Shinji Ogawa
Akio Kinoshita
Kenichi Naka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP55047549A priority Critical patent/JPS5836382B2/en
Publication of JPS56145448A publication Critical patent/JPS56145448A/en
Publication of JPS5836382B2 publication Critical patent/JPS5836382B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To achieve the effective processing by CPU by providing the function of diagnosing periodically CPUs which correspond to respective couplers, that of informing other couplers of the fault occurence of CPU, and that of rearranging the contents of its own reserve register. CONSTITUTION:To CPU buses 3-1-3-3 of CPUs 1-1-1-3 of the multisystem computer system, couplers 2-1-2-3 are connected and at the intersections of buses 3-1-3-3 and common-use buses 4-1 and 4-2, bus switches S11-S32 are provided. Those couplers 2-1-2-3 are provided with microprocessor 7, bus control circuit 8, sequence control circuit 9, and data-reception/transmission control circuits 10 and 11, and main memory 13 of the processor is further connected via microprocessor bus 12. Under the control of processor 7, the fault of one of CPUs 1-1-1-3, when occurring, is reported to other couplers 2-1-2-3 to rearrange the contents of its own reserve register, thereby making the processing of other CPUs effective.
JP55047549A 1980-04-11 1980-04-11 Shared bus control method Expired JPS5836382B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55047549A JPS5836382B2 (en) 1980-04-11 1980-04-11 Shared bus control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55047549A JPS5836382B2 (en) 1980-04-11 1980-04-11 Shared bus control method

Publications (2)

Publication Number Publication Date
JPS56145448A true JPS56145448A (en) 1981-11-12
JPS5836382B2 JPS5836382B2 (en) 1983-08-09

Family

ID=12778228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55047549A Expired JPS5836382B2 (en) 1980-04-11 1980-04-11 Shared bus control method

Country Status (1)

Country Link
JP (1) JPS5836382B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63213035A (en) * 1987-03-02 1988-09-05 Mitsubishi Electric Corp Control method for programmable controller

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61198094A (en) * 1985-02-28 1986-09-02 Fuji Electric Co Ltd Photoelectric switch
JPS62292566A (en) * 1986-06-11 1987-12-19 西武鉄道株式会社 Crossing obstructing detector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63213035A (en) * 1987-03-02 1988-09-05 Mitsubishi Electric Corp Control method for programmable controller

Also Published As

Publication number Publication date
JPS5836382B2 (en) 1983-08-09

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