JPS56145452A - Control system for power source fault of multiprocessor processing system - Google Patents

Control system for power source fault of multiprocessor processing system

Info

Publication number
JPS56145452A
JPS56145452A JP4899680A JP4899680A JPS56145452A JP S56145452 A JPS56145452 A JP S56145452A JP 4899680 A JP4899680 A JP 4899680A JP 4899680 A JP4899680 A JP 4899680A JP S56145452 A JPS56145452 A JP S56145452A
Authority
JP
Japan
Prior art keywords
power source
switching
sw3n
forcible
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4899680A
Other languages
Japanese (ja)
Other versions
JPS5816496B2 (en
Inventor
Hiroshi Maruoka
Kunikazu Imai
Akihiko Suzuki
Hiroyuki Abiko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP55048996A priority Critical patent/JPS5816496B2/en
Publication of JPS56145452A publication Critical patent/JPS56145452A/en
Publication of JPS5816496B2 publication Critical patent/JPS5816496B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Abstract

PURPOSE:To continue the condensed operation of a normal system by performing forcible switching without the processing delay of stored program control, by using an independently controllable switching device in emergency processing such as the failure of a main power source. CONSTITUTION:Switching devices SW11-SW3n controllable independently of one another are provided corresponding to intersections between CPU processing system buses 2-1-2-3 and peripheral-device system buses 5-1-5-n, and between CPUs 1-1-1-3 and peripheral device systems 4-1-4-n, power source control part 11 for main power source A or B is provided. To control part 11, power source controller 10 is connected and constitution processor 8 for the multiprocessor processing system is composed of switching devices SW11-SW3n. The control part 11 is provided with a bus-forcible-switching processing circuit which sends a bus-forcible-switching signal to switching devices SW11-SW3n when a main-power source supply setting circuit and power source A ro B to change power sources A and B over without the program control of device 10.
JP55048996A 1980-04-14 1980-04-14 Power supply abnormality control method for multiprocessor processing system Expired JPS5816496B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55048996A JPS5816496B2 (en) 1980-04-14 1980-04-14 Power supply abnormality control method for multiprocessor processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55048996A JPS5816496B2 (en) 1980-04-14 1980-04-14 Power supply abnormality control method for multiprocessor processing system

Publications (2)

Publication Number Publication Date
JPS56145452A true JPS56145452A (en) 1981-11-12
JPS5816496B2 JPS5816496B2 (en) 1983-03-31

Family

ID=12818811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55048996A Expired JPS5816496B2 (en) 1980-04-14 1980-04-14 Power supply abnormality control method for multiprocessor processing system

Country Status (1)

Country Link
JP (1) JPS5816496B2 (en)

Also Published As

Publication number Publication date
JPS5816496B2 (en) 1983-03-31

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