JPS56143073A - Multiprocessor processing system - Google Patents

Multiprocessor processing system

Info

Publication number
JPS56143073A
JPS56143073A JP4702180A JP4702180A JPS56143073A JP S56143073 A JPS56143073 A JP S56143073A JP 4702180 A JP4702180 A JP 4702180A JP 4702180 A JP4702180 A JP 4702180A JP S56143073 A JPS56143073 A JP S56143073A
Authority
JP
Japan
Prior art keywords
constitution
bus
cpu
power supply
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4702180A
Other languages
Japanese (ja)
Other versions
JPS5816494B2 (en
Inventor
Hiroshi Maruoka
Kunikazu Imai
Akihiko Suzuki
Hiroyuki Abiko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP55047021A priority Critical patent/JPS5816494B2/en
Publication of JPS56143073A publication Critical patent/JPS56143073A/en
Publication of JPS5816494B2 publication Critical patent/JPS5816494B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To increase reliability of an entire system, by providing a bus of CPU system with a constitution controller monitoring the state of CPU and a constitution processor controlling a switching device located at the cross point between the bus of a peripheral device system and the bus of the CPU system. CONSTITUTION:The buses 2-1-2-m of CPUs 1-1-1-m system are provided with the constitution controllers 7-1-7-m which make reception/transmission of information among CPUs. Further, the constitution processor 8 having the status monitor 11 which monitors the state of the power supply control section 13 making application/ cut-off of the power supply to the PF system, connection switching section 9 controlling the switching devices SW11-SWmn provided at the cross point between the CPU system bus and the peripheral device PF system buses 5-1-5-n, and the PF system and the switching device SW, is provided. The monitor section 11 stores the preceding status information of PF and SW to the memory, and compares the memory information and the status information of the newest PF or SW. If they are in disagreement, it is informed to the data processing section of the stored program control by interruption to switch SW and cut-off of the power supply of PF, to avoid influence of one failure on other parts.
JP55047021A 1980-04-10 1980-04-10 multiprocessor processing system Expired JPS5816494B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55047021A JPS5816494B2 (en) 1980-04-10 1980-04-10 multiprocessor processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55047021A JPS5816494B2 (en) 1980-04-10 1980-04-10 multiprocessor processing system

Publications (2)

Publication Number Publication Date
JPS56143073A true JPS56143073A (en) 1981-11-07
JPS5816494B2 JPS5816494B2 (en) 1983-03-31

Family

ID=12763521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55047021A Expired JPS5816494B2 (en) 1980-04-10 1980-04-10 multiprocessor processing system

Country Status (1)

Country Link
JP (1) JPS5816494B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0693723A1 (en) * 1994-07-13 1996-01-24 Advanced Micro Devices, Inc. Power management in a computer system
CN102678348A (en) * 2011-03-15 2012-09-19 罗伯特·博世有限公司 Device possessing a control system for control device
CN109189699A (en) * 2018-09-21 2019-01-11 郑州云海信息技术有限公司 Multipath server communication means, system, middle controller and readable storage medium storing program for executing

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0693723A1 (en) * 1994-07-13 1996-01-24 Advanced Micro Devices, Inc. Power management in a computer system
US5596756A (en) * 1994-07-13 1997-01-21 Advanced Micro Devices, Inc. Sub-bus activity detection technique for power management within a computer system
CN102678348A (en) * 2011-03-15 2012-09-19 罗伯特·博世有限公司 Device possessing a control system for control device
CN102678348B (en) * 2011-03-15 2017-08-29 罗伯特·博世有限公司 Equipment with the control system for control device function
CN109189699A (en) * 2018-09-21 2019-01-11 郑州云海信息技术有限公司 Multipath server communication means, system, middle controller and readable storage medium storing program for executing
CN109189699B (en) * 2018-09-21 2022-03-22 郑州云海信息技术有限公司 Multi-server communication method, system, intermediate controller and readable storage medium

Also Published As

Publication number Publication date
JPS5816494B2 (en) 1983-03-31

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