JPS5816494B2 - multiprocessor processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a multiprocessor processing system, particularly a multiprocessor processing system in which a plurality of central processing units share a plurality of groups of peripheral devices, in which the status of each of the devices in the system is monitored. While monitoring, it is possible to improve the reliability of the system by dealing with failures in one of the central processing units, for example, or failures in the management device itself that manages the on/off status of the central processing unit bus line and the peripheral device bus line. The present invention relates to a multiprocessor processing system.

In order to improve the reliability and processing capacity of data processing systems, multiple central processing units and multiple groups of peripheral devices are combined, so that even when one central processing unit goes down, other central processing units can Efforts are being made to enable backup or parallel processing using multiple central processing units.

In the case of such a system configuration, a management device is required to manage the connection state so that commands are not received simultaneously from a plurality of central processing units for one peripheral device system.

For this reason, the reliability of the system cannot exceed the reliability of the management device itself.

In addition, multiple central processing units/devices share multiple peripheral device systems to provide flexibility in system operation; for example, one central processing unit is linked to one peripheral device system. It is necessary to ensure that the advantages of the system itself do not become counterproductive due to a failure of the underlying central processing unit itself or a failure of the peripheral device system itself.

FIG. 1 shows an example of the conventional configuration of this type of multiprocessor processing system, in which reference numerals 1-1, 1-2 are central processing units, 21 and 2-2 are central processing unit bus lines, respectively. Reference numeral 3 represents a management device, 4-1 to 4-n each a switching device, 5-1 to 5-n each a peripheral device system bus line, and 6-1 to 6-n each a peripheral device system.

Needless to say (, all of the multiple central processing units are #1
By controlling the switching device 4-1, the busbars 2-1 or 2-2 and 5
-1 to perform processing in conjunction with the peripheral device system 6-1.

At this time, the management device 3 manages that, for example, the central processing unit 1-1 is connected to the #1 switching device 4-1, and the other central processing unit 1-2 undesirably switches to the #1 switching device 4-1. The switching device 4-1 and the central processing unit 1-1 are disconnected from each other so that they are not connected to each other.

However, in the case of such a conventional system, if a failure occurs in the management device itself, there is a risk that the entire system will go down.

In addition, the management device 3 and each switching device 4-1 to 4-n draw in the central processing unit busbars 2-1 and 2-2, respectively.
For this reason, when a failure occurs in the management device 3 or any of the switching devices, it is not easy to disconnect it.

In particular, even in the case of a fault in a switching device, there is a problem in that the faulty switching device cannot be easily disconnected while the system is still in operation.

Furthermore, when operating the system, it is necessary to constantly monitor the status of a large number of devices in the system, such as the switching device, peripheral devices, etc., in order to operate the system appropriately.

For this reason, various methods have been proposed to monitor the status of a large number of devices as described above, but a condition monitoring method that can monitor the status of a large number of devices with a simpler circuit configuration is strongly desired. ing.

The present invention aims to solve the above-mentioned problems, and the multiprocessor processing system of the present invention has the following features:
In a multiprocessor processing system in which a plurality of central processing units and a plurality of groups of peripheral device systems are linked by turning each central processing unit bus line and each peripheral device system bus line on and off via a switching device, each of the above-mentioned A configuration control device is provided corresponding to the central processing unit bus line and performs information exchange between each central processing unit and status monitoring of each central processing unit, and also includes a configuration control device that is provided corresponding to the central processing unit bus line and each central processing unit bus line and each peripheral device. A connection switching unit that cuts the switching device provided corresponding to the intersection with the system bus, a power control unit for turning on and off the power to the peripheral device system, and a power supply control unit that is stored in memory in advance. at least the peripheral device system; and a configuration processing device having a status monitoring unit that monitors changes in the status of each of the devices by sequentially comparing previous status information of each of the switching devices and the latest status information of each of the devices. The status monitoring unit includes a stored program controlled data processing unit, a memory for storing status information, and a comparison processing unit, and writes status information of the peripheral device system and the switching device to the memory. The previous state information read from the memory and the latest information of the peripheral device or switching device corresponding to the information are compared in the comparison processing section, and when there is a discrepancy, the data processing section is interrupted and notified. There is.

This will be explained below with reference to the drawings.

FIG. 2 shows the configuration of an embodiment of the present invention, FIG. 3 shows the configuration of an embodiment of the configuration processing device shown in FIG. 2, and FIG. 4 shows an embodiment of the status monitoring unit shown in FIG. 3. Show the configuration.

In FIG. 2, symbols 11, 1-2, 2-1°2-2.
5-1 to 5-n and 6-1 to 6-n correspond to FIG. 1, respectively, and 7-1 and 7-2 respectively indicate a configuration control device;
Reference numeral 8 represents a configuration processing device, 5W11 to 5W2n each a switching device, and 11 a control line.

In the case of the present invention, the switching devices 4-1 to 4- shown in FIG.
In place of n, switching devices 5W11 to 5W2n are independently provided at positions corresponding to the intersections of each central processing unit bus 2-1, 2-2 and each peripheral device bus 5-1 to 5-n, respectively. There is.

These are controlled by a configuration processing device 8 as described later with reference to FIG. 3, and the management device 3 shown in FIG. The functions are distributed to the device 8.

Each configuration control device 7-1, 7-2 manages the state of connection with the peripheral device system of the corresponding central processing units 1-1, 1-2, and the state of each corresponding central processing unit.

For example, when a failure occurs in the central processing unit 1-1, the #1 configuration control device 7-1 notifies the configuration processing device 8 of this fact, and also sends a notification to the central processing unit 1-1 via the #2 configuration control device 7-2. Notify 2.

As will be described later with reference to FIG. Control device 7-1, 7-
Based on the information from 2, each switching device 5W11 to 5
Controls W2n.

That is, the switching control in the switching devices SW1□ to SWln is performed by the central processing unit 1-1 via the bus 2-1 and by the manual configuration control unit in the configuration processing unit 8 as shown in FIG. When a failure occurs in the processing device 1-1, this state is detected by the #1 configuration control device 7-1, and this fact is notified to the configuration processing device 8 and #2 configuration control device 7-2 via the control line 11. .

As a result, the configuration processing device 8 turns off the power to the switching devices SW1□ to 5W1n, so that each switching device SW1 to 5W1 from the central processing unit 1-1
Disable switching control for n.

Further, the central processing unit 1-2 notified via the #2 configuration control device 7-2 continues processing in place of the central processing unit 1-1 as necessary.

FIG. 3 shows an embodiment of the configuration of the configuration processing apparatus shown in FIG.

Codes 1-1 to 1-m, 2-1 to 2-m in the figure
, 5-1 to 5-n, 6-1 to 6-n, 7-
1 to 7-m, 8. SWl to SWmn correspond to FIG. 2, respectively.

Reference numeral 9 is a connection switching unit that includes the switching devices SW1□ to SWmn, and 10 is a manual configuration control unit that allows the operator to manually control each of the switching devices SW1 to SWmn.
11 is a status monitoring unit that enables the Wmn to be turned on and off, and the unit 7-1 is a state monitoring unit that monitors the power status of each unit and each configuration control unit 7-1.
Based on information from 7-m (central processing unit 1-1
or 1-m, the switching device 5W11
12 is a status display unit that displays the on/off status of the switching device 5W11 to SWmn, and 13 is a power supply control unit #1 to # provided for each peripheral device system. n power supply control unit 13
-1 to 13-n control and management, 14
-1 and 14-2 are husband and wife main power supplies that obtain DC voltage from mutually independent input AC 100V power supplies, i
s-i 1 to 15-mn are sub power supplies, respectively, which are supplied with power from the two main power supplies 14-1 and 14-2 and supply power to the corresponding switching devices 5W11 to SWmn, 12 to 17; each represents a control line.

The power supplies in the configuration processing device 8 are #1 main power supply 14-1 and #2
It has a redundant configuration with a main power source 14-2, and the configuration processing device 8 is configured to operate correctly even in the event of a failure of either one of the main power sources.

#11 for each switching device SW1 to SWmn
Sub-power supplies 15-11 to #mnmn are connected to the sub-power supplies 15-1, and if one of the switching devices fails or for some other reason it becomes necessary to disconnect one of the switching devices from the system. In such cases, it is sufficient to disconnect only the corresponding sub-power supply from the power supply.

The illustrated switching devices SW1 to SW m n are individually switched on and off by a manual configuration control 10 via a control line 12 .

Further, the switching devices SW1□ to 5W1n are individually turned on and off by the central processing unit 1-1 via the bus 2-1 within a range that does not affect the processing by other central processing units.

Similarly, the switching devices SW2 to 5W2n are turned on and off by the central processing unit 1-2, and the switching devices SWm1 to SW mn are turned on and off by the central processing unit 1-m. .

The influence on the processing of other central processing units is as follows:
1 to 7-m are managed by communicating via the control line (1).

If a failure occurs in one central processing unit, for example, 1-1, there is a possibility that all peripheral device buses connected to the bus 2-1 at that time may become unusable by other central processing units.

For this reason, when the #1 configuration control device 7-1 detects a failure in the central processing unit 1-1, the #1 configuration control device 7-1
notifies the other component control devices of the occurrence of the failure via the control line 11, and also notifies the status monitoring unit 11 shown in FIG.

As a result, the state monitoring section 11, as described later with reference to FIG.
n Instructs to disable the KJj control.

Note that the auxiliary power supply 15-11 or 15-In may be turned off as necessary.

The operation of each of the switching devices 5W11 to SW, n is displayed on the status display section 12.

Further, when a power supply abnormality occurs in any of the sub power supplies 15-11 to 15-mn, for example, the state monitoring unit 11 is notified of this via the control line 16.

In the status monitoring unit 11, depending on the contents, the sub power supply 15
-11, the central processing unit 1 checks the switching device 5W11 supplied with power and controls the switching device SW1□.
-1 via the #1 configuration control device 7-1.

Furthermore, if a power supply abnormality occurs in the peripheral device system, for example 6-n, this fact is notified to the status monitoring section 11 via the control line 17.

The status monitoring unit 11 instructs the connection switching unit via the control line 13 to disconnect the peripheral device system bus 5-n, which is connected to the peripheral device system 6-n, from the system.
It notifies each central processing unit 1-1 to 1-m via.

As explained above, the state monitoring section 11 must monitor changes in the state of each device and always keep track of the latest state information.

In FIG. 4 showing an embodiment of the configuration of the condition monitoring section 11 according to the present invention, reference numeral 11 in the figure indicates a condition monitoring section, Pl.
to Pn are state monitoring devices, and in FIGS. 2 and 3, peripheral device systems 6-1 to 6-n, switching devices SW1° to SWmn, sub-power supplies 15-11 to 15-mn, power supply systems (finance control), ) Units 13-1 to 13-n
16 is a data selector, 1γ is an address counter, 18 is a memory, 19 is a comparison circuit, 2
0 represents an interrupt request circuit, and 21 represents a data processing section.

Also, S11. S12. ......Sum or Sn1, Sn2, ......Snm is status information of the status monitoring device P1 to Pn, ADD is an address signal, NS is latest status information, O8 is Previous state information, REQ represents an interrupt request signal, and DT represents state change information, respectively.

In FIG. 4, consecutive addresses are set for the state monitoring devices P1 to Pn, and status information S11, S12, etc. of each of the state monitoring devices P1 to Pn.
...S1m or Sn1, Sn2...
. . .Snm is stored in advance in the memory 18 in correspondence with the above address in accordance with the operation of the status monitoring unit 11, which will be described later.The operation of the status monitoring unit 11 will now be described.

(1) In the data selector 16, according to the address signal ADD indicated by the address counter 17, the state information of the state monitoring device corresponding to the address signal ADD is determined, for example, the address signal ADD indicates the state monitoring device P1. If there is, status information SK at that time
I + Si2...The latest state information of S1m is selected.

Then, assuming that the latest state information is NS, the latest state information NS is sent to the comparison circuit 19.

(11) At the same time as the upper fitting 1), the address signal AD
The address signal ADD in the memory 18 according to D
The information stored in advance at the address corresponding to , that is, the previous state information O8 of the state monitoring device P1 is read out and sent to the comparison circuit 19.

(11*) In the comparison circuit 19, the latest state information NS of the state monitoring device P1 and the previous state information O8
are compared.

θψ If a mismatch is detected as a result of the comparison in the comparison circuit 19, the interrupt request circuit 20 issues an interrupt request to the data processing unit 21, and when the interrupt request is accepted, the latest state information NS or the previous State change information corresponding to state information O8 is sent to address counter 1.
7, that is, the address signal AD of the state monitoring device P1.
The data processing unit 21 is notified together with D.

Further, the latest status information NS is written to the address of the status monitoring device P1 on the memory 18.

(■) When the operation of the upper value +V+ is completed, or above;
If the result of an) matches, the address counter 17 is incremented and the state change of the next predetermined state monitoring device, for example P2, is monitored.

The state monitoring unit 11 according to the present invention can monitor changes in the state of a large number of state monitoring devices P1 to Pn by repeating the operations (1) to V) described above.

That is, the status of a large number of devices can be efficiently monitored using a simple circuit configuration as shown in FIG.

As explained above (according to the present invention, each configuration control device 7
is received in response to the valley central processing unit 1, and communicates the status of the central processing unit, etc., and the switching devices 5W11 to SWm
They are provided independently corresponding to the intersections of n bus lines 2 and 5, so that bacteriostatic control from the central processing unit side and bacteriostatic control from the constituent processing unit 8 side can be performed independently.

For this reason, the reliability of the system is improved, and the reliability of the configuration processing unit 8 itself is improved by, for example, having a dual configuration of the power supply within the configuration processing unit 8, thereby improving the reliability of the entire system. .

It goes without saying that control lines 11 and the like have a dual configuration.

Furthermore, the status monitoring unit 11 that monitors status changes of each device in the system uses a circular scanning method to detect status changes with a simple circuit configuration, and performs bacteriostatic control in response to the status changes, thereby further improving bacteria control. It is possible to improve the reliability of the entire system.

[Brief explanation of the drawing]

Figure 1 shows an example of a conventional multiprocessor processing system.
FIG. 2 shows the configuration of an embodiment of the present invention. 3 shows an embodiment of the configuration of the configuration processing device shown in FIG. 2, and FIG. 4 shows an embodiment of the configuration of the state monitoring section shown in FIG. 3. In the figure, 1 is a central processing unit, 2 is a central processing unit bus line, 5 is a peripheral device system bus line, 6 is a peripheral device system, 7 is a configuration control device,
8 is a configuration processing device, 9 is a connection switching unit, 10 is a manual configuration control unit, 11 is a status monitoring unit, 12 is a status display unit, 13 is a power supply side surgical unit, 14 is a main power supply, 15 is a sub power supply, 16 is a 17 is an address counter, 18 is a memory, 19 is a comparison circuit, 20 is an interrupt request circuit, and 21 is a data processing section. Further, Pl to Pn each represent a state monitoring device.

Claims (1)

[Claims] 1. In a multiprocessor processing system in which a plurality of central processing units and a plurality of groups of peripheral device systems are linked by turning each central processing unit bus line and each peripheral device system bus line on and off via a switching device, the above-mentioned A configuration control device is provided corresponding to each central processing unit bus line and performs information exchange between each central processing unit and status monitoring of each central processing unit, and a configuration control device is provided corresponding to each central processing unit bus line and each peripheral A connection switching section for controlling a switching device provided corresponding to the intersection with the device system bus line, a power supply control section for turning on and off power to at least the above-mentioned peripheral device system, and a small number stored in memory in advance. (Includes a configuration processing device having a status monitoring unit that monitors changes in status of each of the devices by sequentially comparing previous status information of each of the peripheral device system and the switching device with the latest status information of each device. , and the status monitoring unit includes a data processing unit under stored program control, a memory for storing status information, and a comparison processing unit, and writes status information of the switching device to the memory in the case of the peripheral device system. The previous state information read from the memory and the latest information of the peripheral device or switching device corresponding to the information are compared in the comparison processing section, and when there is a discrepancy, the data processing section is interrupted and notified. A multiprocessor processing system characterized by: