JP3750146B2 - Horizontally distributed network system - Google Patents

Description

【００７４】
まず、表１のＮo.１は、鉄道交通システムの鉄道路線の情報制御に本発明を適用したものである。対象となる路線内で核となる主要な駅（あるいは制御室）の情報処理機器を、路線全域に渡る共有バスに接続し運行情報などを通信する。また、各々の核駅間を個別バスで結合し、核駅間に存在する地方駅や信号機，遮断機を、個別バスに接続されるＩ／Ｏとすることで、路線全域の運行管理や制御を行うものである。なお、個別バスに接続される入出力機器として情報端末機器などを接続することで、座席予約システムなどの情報通信ネットワークとしても応用が可能である。
【００７５】
本応用例では路線全域に渡る共有バスの故障に対しても、複数の個別バスを経由して情報を通信できると共に、核駅にある情報処理機器の故障に対しても、個別バスで接続された他の核駅にある情報処理機器がバックアップできる構成となるため、バスおよび情報処理機器の故障においてもシステムを停止することなく連続運転が可能となる効果がある。
【００７６】
次に、表１のＮo.２は鉄道車両の車両内制御装置に本発明を適用した例であり、図１２に詳細な応用例を示す。連結された車両数をｎとし、各車両毎の制御装置を全車両共通の共有バス２で結合すると共に、各車両に設けた車両制御部１１.１〜１１.ｎの相互を複数の個別バス３.１〜３.ｎで結合する。各個別バスに接続される機器としては車両毎に異なるが、扉制御，空調機制御，照明制御，駆動モータ制御装置といった下位の制御部がある。共有バス２には車両速度指令や、各車両毎の温度設定値などが通信され、それぞれの指令値に従い各車両内の制御装置が処理を実行する。
【００７７】
なお、図１２において最後尾車両の個別バス３.ｎと先頭車両の個別バス３.０を接続することにより、各個別バスに接続される全ての機器は２つの車両制御部から制御可能となり、車両制御部の故障に対しても運転の継続が実現できる。なお、共有バスで伝送される情報としては、ラジオ回線や電話回線などの車内サービスとしても利用できる。なお、本応用において各車両制御部は車両内全ての下位の制御部を管理しているが、他の車両にある下位の制御部を分担するなど、その分担方法は自由に設定できることは明らかである。
【００７８】
次に、表１のＮo.３は鉄鋼の圧延設備において、複数の圧延スタンド制御に本発明を適用した例である。複数圧延スタンドの個々に設置された制御装置を共有バスで結合すると共に、各個別バスには各々の圧延スタンドを制御する圧延ロール駆動装置や圧下駆動装置などが接続される。全圧延スタンド間にまたがる共有バス２には、各圧延スタンドのロール速度や圧下速度といった各種指令値、あるいは各圧延スタンドの運転状況などの情報が通信され、複数の圧延スタンド間の協調制御が実現できる。
【００７９】
本応用例では、複数の圧延スタンドの制御装置のうち、１つの制御装置が故障した場合のバックアップが可能になる他、個別バスにより２つの圧延スタンド間でのキメ細かな情報通信ができるため、圧延スタンド間の協調制御が容易になる効果がある。
【００８０】
表１のＮo.４は、製鉄所において上述のＮo.３よりも更に上位の圧延設備に本発明を適用した例である。製鉄所における加熱炉や圧延機をはじめとする各種設備に設けられている制御部を共有バスで接続し、製鉄所内の各設備の運転指令や運転状況などの情報が通信される。また、各設備間を結合する個別バスには各設備内の下位の制御装置、例えば加熱炉の温度制御装置あるいは圧延機の板厚制御装置や張力制御装置などを接続するものである。なお、本例に示した個別バスを上記Ｎo.３に示した圧延設備の共有バスとして上記Ｎo.３のシステムを接続することで、Ｎo.４のシステムを上位としＮo.３のシステムを下位とした、製鉄所における圧延機制御システムを、図９に示す階層構造を持つシステムに構築できる。
【００８１】
表１のＮo.５は火力発電所の設備に本発明を適用した例である。火力発電所におけるボイラやタービンをはじめとする各種設備に設けられている制御部を共有バスで接続し、発電所内の各設備に対する運転指令や運転状況などの情報が通信される。また、各設備間を結合する個別バスには各設備内の下位の制御装置、例えばボイラの蒸気圧制御装置や温度制御装置、あるいはタービンのタービン圧力制御装置などが接続されるものである。
【００８２】
表１のＮo.６は広域な計算機ネットワークシステムに本発明を適用した例として、銀行のオンラインシステムについて説明する。銀行の本店や各支店に設置された計算機の全てを共有バスで結合すると共に、個別バスは距離的に近い支店間（あるいは本店と支店間）を相互に結合するものである。また、個別バスには、本店あるいは支店に設置されたオンラインＣＤ端末や窓口端末、または、本店あるいは支店が管轄する出張所の端末機器が接続される。
【００８３】
従って、各端末機機は２つの計算機による管理が可能になると共に、全国規模の情報通信には共有バスを用い、特定地域での比較的狭い地域での情報通信には個別バスを用いることで、顧客に対して高速なサービスを提供できるという効果がある。
【００８４】
表１のＮo.７は狭い範囲における計算機ネットワークシステムに本発明を適用した例として、建屋内ＯＡシステムのネットワークについて説明する。共有バスには建家内のトータルシステムを管理するホストの計算機と、各階に設置されたネットワークコントローラが接続される。これらネットワークコントローラから出力される個別バスは、各階に配線され他の上下階のネットワークコントローラと結合される。従って、各階に設置されるワークステーションやパソコン，プリンタなどのＯＡ機器は２つの階にあるネットワークコントローラから管理されることができるため、ネットワークコントローラの故障に対しても各ＯＡ機器は運転を続行できる構成となる。
【００８５】
表１のＮo.８は本発明を適用したマルチプロセッサを用いた機器の制御装置として、モータ制御装置に応用したシステムについて説明する。また、制御装置における制御ユニットのプリント回路板、あるいはバスの配線方法の具体例を図 １３に示す。本例におけるモータ制御装置の演算部としては、速度制御や電流制御など各制御ブロック毎にマイコンを用いたマルチプロセッサシステムを構成しており、各々の演算部あるいは機能毎の入出力回路が１枚のプリント回路板で実現されている。個別バスに接続される入出力回路としては、電流検出回路などのアナログ信号処理回路や、エンコーダパルスの処理回路あるいは電力変換器へのＰＷＭパルス出力回路などがあり、各々のプリント回路板は制御処理を実行するマイコンに対応した個別バスに接続される。これらプリント回路板の制御ユニットへの実装方法の一例として、図１３のように構成することができる。なお、図１３では複数制御ユニットに拡張できる構成を示しているが、単一ユニットで使用することも可能である。
【００８６】
図１３において２つの制御ユニット５０，６０には、各々３枚のマイコンを含んだプリント回路板（以下、マイコンボードと称す）５１〜５３，６１〜６３と、それらの間に入出力回路のプリント回路板５１１〜５３２，６１１〜６３２が配置されバックボードにより接続される。各制御ユニット内で上述の各プリント回路板が接続されるバックボードには、上部に共有バスが配線されると共に、下部に複数の個別バスがマイコンボード毎に互い違いに配線されることで、マイコンボードと入出力回路が、１つの共有バスと２つの個別バスに接続される。
【００８７】
このような実装方式とすることで、各個別バスおよび入出力回路は、隣合う２つのマイコンボードに共有されることになり本発明の構成を実現できる。なお、全マイコンボードに共通な入出力回路を接続する場合には、入出力回路内に共有バスインターフェイスを設けてバックボードと接続することで実現されることは明らかである。また、別の制御ユニットに拡張する方法としては、ドライバやレシーバを含む拡張ユニット５５，６５から出力される拡張バスを接続することで実現される。つまり、共有バスの拡張バスポートであるＣＡ１，ＣＢ１とＣＡ２，ＣＢ２を、また、個別バスの拡張バスであるＬＡ１，ＬＢ１とＬＡ２，ＬＢ２を、それぞれ制御ユニットが直列になるように接続することで、２ユニット以上の拡張が可能である。また、制御ユニットの拡張数を２ユニットに限定した場合には、共有バスの拡張バスは１ポートで充分で各々を直結し、個別バスは２つの拡張ポートのうちＬＡ１とＬＢ２，ＬＢ１とＬＡ２を結合することで全てのマイコンボードがリング状に接続されるため、各々の入出力回路は２つのマイコンで管理されることになる。
【００８８】
なお、本応用例ではモータ制御装置について述べたものであるが、電力変換装置などパワーエレクトロニクス制御装置を始めとする、マルチプロセッサシステムを適用した各種制御装置にも適用可能である。更に、２つの個別バスを２つのマイコンボード間で並行して配線されるようにバックボードを構成した場合には、図１１に示すような個別バスおよび入出力回路をも２重化した制御装置の構成を、同一仕様のマイコンボードで実現することができる。
【００８９】
表１のＮo.９は道路を通行する自動車通行量を監視または制御する、道路交通システムに本発明を適用した例である。道路上の主要交差点に演算部を置き、主要交差点間を接続する個別バスには主要交差点間の信号機や交通量監視装置などを設置する。各地点に設置された交通量監視装置からの交通量、あるいは信号機の操作情報などを共有バスで伝送し、各演算部が信号機を操作することにより交通量を制御し、渋滞の少ないスムーズな通行を実現できる。
【００９０】
表１のＮo.１０は電力ネットワークシステムにおいて、特に家庭への給電システムに本発明を適用した例を説明する。複数の配電所は共通の電力母線から電力が供給され、配電所間を結ぶ支線から各家庭に電力を供給するものである。つまり、支線には複数の柱上トランスが設置され、柱上トランスから各家庭へ所定の電圧を供給するものである。
【００９１】
従って、各支線は２か所の配電所から電力の供給が可能となる電力ネットワークシステムを構築でき、配電所の故障に対しても各家庭への停電を防止することができる。また、配電所から出力する支線を３本とし、うち１本を他の電力ネットワークシステムの配電所と結合し、つまり図１０に示しすように複数の電力ネットワークシステムを結合する構成とすることで、１つの電力ネットワークシステムの電力母線が故障した場合においても、他の電力ネットワークシステムの電力母線から配電所を介して電力の供給を続行できる電力ネットワークシステムを実現できる。
【００９２】
【発明の効果】
本発明によれば、複数の制御演算機能を有するネットワークシステムにおいて、共有バスと個別バスを有する２重バス構成であり、各制御演算機能に固有な入出力回路を個別バスに接続することで、バス上の競合が少ない高速なシステムを可能とし、各々の個別バスは２つの制御演算機能と接続され共有されるために、各個別バスに接続された入出力回路は一方の制御演算機能が故障した場合にも、他の一方の制御演算機能からもアクセスできるため、制御演算機能の故障に対しても個別バスと接続された正常な制御演算機能が故障した制御演算機能の制御処理を引き継ぐことが可能となり、制御演算機能の故障に対しても多重化あるいは冗長化することなく最小限の構成でシステムの無停止運転が可能となり、信頼性の高いシステムを構築できるという効果がある。
【００９３】
また、制御演算機能は２つの個別バスインターフェイスを持ち、各々の個別バスインターフェイスは異なる他の制御演算部と直列に接続されるため、全ての制御演算部の構成を標準化でき、システム規模に応じた制御演算機能の拡張が容易に実現できるという効果がある。
【００９４】
また、各々の個別バスは２つの制御演算機能でのみアクセス可能であることから、システム規模が大きくなり制御演算機能の数が増えた場合にも、各制御演算機能の処理能力の低下を抑えることができ、高性能なシステムを実現できるという効果がある。
【００９５】
更に、共有バスと個別バスの２系統の情報通信手段を用いて診断データの出力と判別を行うことにより、演算部の相互診断および共有バスあるいは個別バスの故障診断をソフトウェアで実現できると共に、故障した演算部またはバスのバックアップを、他の演算部あるいはバスで実現できることから、信頼性の高いシステムを構築できるという効果がある。
【図面の簡単な説明】
【図１】本発明を適用したネットワークシステムの一実施例の構成図。
【図２】図１の演算部の構成図。
【図３】図１の演算部が図２で構成され、演算部が故障した場合のバックアップ処理を説明するフローチャート。
【図４】図１の演算部の構成図。
【図５】図１の演算部が図４で構成され、演算部が故障した場合のバックアップ処理を説明するフローチャート。
【図６】本発明の他の実施例であるネットワークシステムの構成図。
【図７】図６のシステムにおける診断方法を説明するフローチャート。
【図８】本発明の他の実施例であるネットワークシステムの構成図。
【図９】本発明の他の実施例であるネットワークシステムの構成図。
【図１０】本発明の他の実施例であるネットワークシステムの構成図。
【図１１】本発明の他の実施例であるネットワークシステムの構成図。
【図１２】本発明を鉄道車両の制御に応用した場合の詳細な構成図。
【図１３】本発明を適用した制御装置における制御ユニット回路の具体的構成図。
【符号の説明】
１.１〜１.ｎ…演算部、２…共有バス、３.０〜３.ｎ…個別バス、４０.ａ 〜４０.ｎ …制御演算処理に用いる入出力回路。[0001]
[Industrial application fields]
The present invention relates to a system having a plurality of computers (including a microcomputer (hereinafter, abbreviated as a microcomputer)), and redundancy in a network system connecting various computers such as a traffic system, a general industrial system, and an in-building information communication system. It relates to an effective system.
[0002]
[Prior art]
Conventionally, many network systems and control devices using a plurality of computers have been announced. Among them, in addition to a shared bus for connecting a plurality of processors and connecting shared resources such as a shared memory, there are two buses of individual buses for connecting individual resources for each processor. As examples realized by the configuration, there are JP-A-4-36854 and JP-A-4-369069.
[0003]
[Problems to be solved by the invention]
In the above prior art, shared resources such as a shared memory, a disk device or an input / output means for information communication between each microcomputer are connected to the shared bus, and the individual bus for each microcomputer controls the control target. Peripheral input / output means unique to each microcomputer can be connected.
[0004]
In addition, by connecting a dedicated communication path that can only communicate between two microcomputers to the individual bus of each microcomputer and performing information communication between the two microcomputers, the amount of communication on the shared bus can be reduced. Performance degradation can be suppressed.
[0005]
However, when one microcomputer breaks down, it has not been devised so that other microcomputers can access the peripheral input / output means connected to the individual bus of the failed microcomputer. You must interrupt the process. That is, there is a problem that in a system in which processing is performed by a plurality of microcomputers, the entire system must be stopped.
[0006]
Conversely, in order not to stop the system even if the microcomputer fails, it is well known that a redundant system is built by multiplexing microcomputers, and when the microcomputer fails, the redundant microcomputer takes over the processing of the failed microcomputer. In this case, it is necessary to prepare a redundant microcomputer that is not normally used, and there is a problem that the scale of the system increases.
[0007]
Furthermore, there is only one shared bus for all the microcomputers. If this shared bus fails, information communication between the microcomputers becomes impossible, so the system must be stopped. Therefore, in order to make the system non-stop even in the case of a shared bus failure, it is necessary to duplicate the shared bus, which causes a problem that the scale of the system increases.
[0008]
The object of the present invention is to minimize the hardware configuration of a system having a large number of computers and microcomputers having a control operation function, and to suppress an increase in the amount of communication on the bus even if the control operation function is increased. In addition to suppressing the performance degradation of individual control operation functions, the control operation function by hardware and software and the diagnosis function of the shared bus and individual bus are used to detect failures early and identify the location of the failure. An object of the present invention is to provide a highly reliable and scalable system that does not stop the system even when a shared bus or individual bus fails.
[0009]
[Means for Solving the Problems]
  To achieve the above object, according to the present invention, in a system in which a target control process is distributed by a plurality of control operation means and executed, each control operation means includes one shared bus interface means, a first and a first Two individual bus interface means, wherein the shared bus interface means is connected to a shared bus that can be commonly used by the plurality of control arithmetic means, and one of the two individual bus interface means. One individual bus interface means is coupled to one individual bus interface means of another specified control operation means by a first individual bus, and the other second individual bus interface means is the first individual bus interface means. One individual bus interface means of the specified control arithmetic means different from the control arithmetic means coupled to the bus Are coupled by a second individual bus, the plurality of control arithmetic means are connected in series by a plurality of individual buses, and the control bus has a bus duplicated by the shared bus and a plurality of individual buses, The calculation means can input information to the other control calculation means connected to the first individual bus via the first individual bus, and the other control calculation means uses the first individual bus. Information can be input to the control arithmetic means connected to the first individual bus via the second individual bus, and the control arithmetic means can receive another control connected to the second individual bus via the second individual bus. Information can be input to the calculation means, and another control calculation means connected to the second individual bus can input information to the control means via the second control calculation means. The individual bus and the second individual bus have input devices or outputs. It is characterized in that the device is connected.
[0012]
[Action]
In a system consisting of a plurality of control operation functions, when information communication between the control operation functions and unique input / output information for each control operation function are realized using only one shared bus, As the amount of data communication increases, bus contention among the control operation functions increases, resulting in a decrease in processing performance. As a countermeasure, a shared bus is used for information communication between control arithmetic functions or communication of input / output information common to each control arithmetic function, and input / output information unique to each control arithmetic function is connected to an individual bus. By realizing dual buses with shared buses and individual buses, it is possible to suppress an increase in the amount of information communication on the shared bus, so there is less overhead for information communication even when the control calculation function is expanded. It is possible to prevent performance degradation. Furthermore, by providing two individual bus interfaces for each control operation function and connecting adjacent control operation functions in series, the control operation function can be easily expanded.
[0013]
In addition, as described above, two individual bus interfaces are provided for each control operation function, and adjacent control operation functions are connected in series, so that one individual bus is shared by two control operation functions. Will be. That is, the input / output means connected to each individual bus is shared by the two control arithmetic functions. Therefore, even if a certain control arithmetic function accesses the input / output means via the individual bus and a failure occurs when the operation is executed, the control arithmetic function that is connected to the faulty control arithmetic function is not connected to the individual bus. Because the same input / output means connected to the individual bus can be accessed instead of the failed control operation function, the operation can be continued without stopping the system.
[0014]
In addition, since the two individual buses of each control arithmetic unit are connected in series with all the control arithmetic functions, each control arithmetic unit communicates information with two adjacent control arithmetic units via the individual bus. It is possible to have two systems of information communication functions together with the shared bus, and communication data on the shared bus can be communicated on the individual bus by using the information communication system using the individual bus even when the shared bus fails. Therefore, it is possible to back up against a shared bus failure.
[0015]
Furthermore, each arithmetic unit outputs a predetermined diagnosis data to a storage means connected to both the shared bus and the individual bus, or outputs diagnostic data directly to another control arithmetic unit, and each control arithmetic unit. The unit captures the diagnostic data output from the other control arithmetic units from the shared bus and the individual bus, and compares and judges the diagnostic data of both, thereby allowing mutual diagnosis between adjacent control arithmetic units and the shared bus and each individual bus. The bus diagnosis can be realized by software. Further, by disconnecting the failed control calculation means or the failed bus from the normal bus or the normal control calculation means, an error signal is generated from the failed control calculation means or the failed bus to the normal bus or the normal control calculation means. Since the intrusion does not occur, backup processing performed by a normal bus or normal control calculation means can be executed correctly.
[0016]
【Example】
An embodiment of a network system using the present invention will be described below with reference to FIG. FIG. 1 is a configuration diagram of a network system in which processing of a target system is distributedly processed by a plurality of arithmetic units 1.1 to 1.n. In this system, necessary information is communicated or stored between the plurality of arithmetic units 1.1 to 1.n via the shared bus 2, and various storage means such as a magnetic memory and an IC memory are used. It is done. Obviously, these storage means may be arranged independently on the shared bus, or may be arranged dispersedly on each arithmetic unit. Although not shown in FIG. 1, an arbitration circuit (bus arbiter) that does not cause bus contention on the shared bus 2 is provided in the arithmetic units 1.1 to 1.n or other circuits connected to the shared bus 2. include.
[0017]
Each of the arithmetic units 1.1 to 1.n includes two individual bus interfaces different from the shared bus 2, and two adjacent arithmetic units are connected to the individual bus 3. Connect in series with 0-3.n. These individual buses 3.0 to 3.n are connected to input / output circuits (I / O circuits) 40.a to 4n.n necessary for control arithmetic processing by the arithmetic unit to which the individual buses are coupled. That is, all the input / output circuits 40.a to 4n.n can be accessed by any two arithmetic units.
[0018]
Here, two arithmetic units connected to a single individual bus have a bus arbitration circuit for each individual bus so that bus contention does not occur when the individual bus is accessed. That is, each of the two individual bus interfaces included in each of the arithmetic units 1.1 to 1.n includes a bus arbitration circuit for the individual bus. Therefore, when all the arithmetic units 1.1 to 1.n are operating normally, each arithmetic unit is based on information from an input / output circuit connected to an individual bus according to a predetermined share. Control arithmetic processing is executed.
[0019]
In such distributed processing, when a certain arithmetic unit fails, another arithmetic unit connected to the failed arithmetic unit via an individual bus takes over the arithmetic processing performed by the failed arithmetic unit. To do. In other words, other normal arithmetic units that are connected to the failed arithmetic unit via an individual bus can access the input / output circuit accessed by the failed arithmetic unit during normal operation. It is possible to take over, and continuous operation can be performed without stopping the system even if the operation unit fails.
[0020]
Further, in the duplex bus configuration using the shared bus and the individual bus shown in the present embodiment, since a plurality of arithmetic units can sequentially transmit information via the adjacent arithmetic units and the individual bus, the shared bus is used. Since the information to be transmitted can be substituted by an individual bus, continuous operation is possible without stopping the system even when the shared bus fails.
[0021]
In addition, as a calculating part in the said Example, it is implement | achieved by what has various calculation functions, such as a microcomputer, as well as a general purpose or a dedicated computer. In addition, the shared bus or individual bus can be realized by either the parallel communication method or the serial communication method. The standard specification such as Ethernet or FDDI has its own dedicated specification. Obviously, either is ok.
[0022]
Furthermore, in addition to information communication means, the shared bus has an input / output circuit common to each control arithmetic unit connected to the shared bus, or an individual bus that can control each arithmetic unit or generate commands to each arithmetic unit It is also possible to connect a higher-order arithmetic unit that does not have. In addition to the input / output circuit, information communication means such as a lower-level control calculation means or storage means can be connected to each individual bus.
[0023]
According to the present embodiment, the information communicated by each arithmetic unit can be divided by the two buses, the shared bus and the individual bus, and the information amount of the shared bus is reduced, so that bus contention among the arithmetic units in the shared bus. As a result, the system performance can be improved. In addition, since the information communication between the two arithmetic units can be performed by the individual bus, the amount of information communication using the shared bus can be reduced, so that an inexpensive (low speed) network protocol can be used. The cost can be reduced. In addition, since there are two buses, if one of the buses malfunctions, information communication can be backed up using another normal bus, so the system reliability can be improved. There is. Furthermore, since the individual bus is divided among a plurality of arithmetic units, even if the individual bus or peripheral input / output circuit fails, the influence of the failed bus does not spread to other individual buses, so the failure is narrow. There is an effect that it can be suppressed to the range.
[0024]
FIG. 2 shows an example of a detailed configuration of the arithmetic unit in FIG. 1, which is a backup circuit configuration when the arithmetic unit fails, and its operation will be described with reference to the flowchart in FIG.
[0025]
The CPU that executes the calculation in the calculation unit of FIG. 2 has a configuration in which a microcomputer is used to allow one adjacent bus to access both adjacent microcomputers to execute calculation processing. The arithmetic unit 1.n has a memory 101 for storing a program and data of the microcomputer 100 that executes the arithmetic operation, and a timing control unit 102 for controlling the timing of peripheral elements in the arithmetic unit. The failure detection unit 103 detects hardware abnormality such as a watchdog timer error, a parity error, an address error and the like in the microcomputer 100 as well as an abnormality in the calculation unit 1.n. The failure detection signal (AB) of the failure detection unit 103 is output to the microcomputer 100 in the own calculation unit to execute processing at the time of failure, and also to the other two calculation units connected to the individual bus. Notify that there is a failure in the calculation unit.
[0026]
The interface means with the shared bus comprises a bus buffer 104 and other arithmetic units and a bus arbiter 105 for avoiding bus contention on the shared bus. When the microcomputer 100 accesses the shared bus, the bus arbiter 105 detects that no other arithmetic unit is using the shared bus, and the bus buffer 104 is activated to enable access to the shared bus. The bus arbiter 105 causes the microcomputer 100 to wait until the shared bus is acquired when another microcomputer is accessing the shared bus when the microcomputer 100 accesses the shared bus. The operation unit is controlled so that the shared bus cannot be accessed.
[0027]
On the other hand, the interface means for the two individual buses a and b include bus buffers 106a and 106b for each individual bus, and bus arbiters 107a and 107b for avoiding bus contention with other arithmetic units on the individual bus. The function is the same as that of the shared bus interface means.
[0028]
When the failure detection unit 103 detects a failure of the own calculation unit, the shared bus buffer 105 and the individual bus buffers 106-a and 106-b are deactivated by a failure detection signal (AB). The faulty computing unit is separated from each individual bus.
[0029]
The processing of the microcomputer .n when another arithmetic unit fails by the arithmetic unit of this configuration will be described with reference to the flowchart of FIG. Note that information communication of each microcomputer is performed using a shared memory connected to a shared bus.
[0030]
As processing contents of the microcomputer .n, first, in step 200, the calculation process shared by the microcomputer .n itself is executed. In step 201, when the microcomputer .n breaks down, another microcomputer .n-1 or microcomputer n + 1 The work data of microcomputer.n is stored in the shared memory so that the process can be backed up. Then, the process regarding microcomputer.n-1 shown in step 202 to step 207 is performed.
In step 202, it is determined by a flag whether or not the microcomputer .n-1 has already failed. If not, the process proceeds to step 203 to determine whether or not a failure detection signal is input from the microcomputer .n-1. If not input, the microcomputer .n-1 is operating normally, and the processing from step 208 is performed on the microcomputer n + 1.
[0031]
On the other hand, when a failure detection signal is input in step 203, the microcomputer .n-1 is immediately after the failure, so in step 204, the work data of the microcomputer .n-1 is fetched from the shared memory. Prepare to execute the process. Thereafter, in step 205, a flag indicating that the microcomputer .n-1 has failed is set, and the process proceeds to step 206.
[0032]
In step 206, the microcomputer .n executes the arithmetic processing shared by the microcomputer .n-1, and the work data is stored in the shared memory in step 207. If the microcomputer .n-1 has already failed due to the flag in step 202, the processing from step 206 is similarly performed. Thereafter, as the processing related to the microcomputer .n + 1, similarly to the processing of the microcomputer .n−1 shown in Step 202 to Step 207, the processing when the microcomputer .n + 1 fails is executed in Step 208 to Step 213. .n + 1 backup is enabled and the process ends.
[0033]
As can be seen from the above description, when a certain microcomputer fails, the processing of the failed microcomputer can be shared by the other two microcomputers connected by two individual buses.
[0034]
According to the present embodiment, since the processing of the failed microcomputer can be shared by the two microcomputers, the increase in the processing of the microcomputer to be backed up can be halved. It has the effect of being suppressed. In addition, by separating the failed computing unit from each bus by the bus buffer, it is possible to prevent an erroneous signal from being output from the failed computing unit to the bus, so that the failure of the computing unit is not propagated elsewhere. There is an effect that the failure range can be suppressed to a narrow range.
[0035]
The detailed configuration of the calculation unit is not limited to that shown in FIG. Therefore, FIG. 4 shows an example of a detailed configuration of the arithmetic unit of FIG. 1, which is a backup circuit configuration when the arithmetic unit fails, and its operation will be described with reference to the flowchart of FIG. 4, the same reference numerals as those in FIG. 2 have the same functions.
[0036]
In this embodiment, of the two individual buses included in each microcomputer, during normal operation, only one individual bus is occupied and accessed to execute arithmetic processing. Accordingly, during normal operation, the other individual bus is occupied by another microcomputer connected by the individual bus. Then, when another microcomputer connected with one other individual bus breaks down, the other one individual bus is switched to be accessible, and the processing of the failed microcomputer is performed by occupying two individual buses. I try to take over. That is, each microcomputer performs a backup operation only for a microcomputer connected by an individual bus that is not accessed during normal operation. Accordingly, during normal operation, the bus buffer 106-b is deactivated by the switch 110-b to disconnect the individual bus b, and the bus buffer 106-a is activated by the switch 110-a. Only the individual bus a is occupied and the control process is executed.
[0037]
Here, when the other arithmetic unit connected to the individual bus b fails, the switch 110-b is connected to the bus buffer by the failure signal AB-r of the other arithmetic unit sent from the individual bus b. By switching 106-b to the operating state, both the individual bus a and the individual bus b are occupied, and the processing of the other operation unit that has failed can be backed up. On the contrary, when the self-processing unit fails, the switch 110-a switches the bus buffer 106-a to the non-operating state by the failure detection signal (AB) output from the failure detection unit 103, so that the individual bus a Disconnect. Accordingly, another arithmetic unit connected to the individual bus a backs up the processing of the own arithmetic unit.
[0038]
Hereinafter, the processing of the microcomputer .n will be described with reference to the flowchart of FIG. It is assumed that a shared memory is connected to a shared bus for information communication of each microcomputer as in the above embodiment.
[0039]
As the processing contents of the microcomputer .n, first, in step 300, the calculation process shared by the microcomputer .n itself is executed. In step 301, when the microcomputer .n breaks down, another microcomputer (in this embodiment, the microcomputer .n- 1), the work data of microcomputer .n is stored in the shared memory so that the process can be backed up. Next, it is checked in step 302 whether or not a failure detection signal for the microcomputer n + 1 has been input. If it has been input, the process proceeds to step 303 to determine whether the microcomputer .n + 1 has already failed. If the failure detection flag is not set in step 303, the microcomputer .n + 1 determines that the failure has just occurred and sets the failure detection flag in step 304.
[0040]
Next, the processing of the microcomputer .n + 1 is succeeded and executed. When each microcomputer is sampled, the processing time increases as much as the burden of the malfunctioning microcomputer is borne. Therefore, after the sampling period of the microcomputer .n + 1 is changed in accordance with the increase of the processing time in step 305, the work data of the microcomputer .n + 1 is taken out from the shared memory in step 306, and the processing is taken over.
[0041]
In step 307, the process of the failed microcomputer.n + 1 is executed, the work data is stored in the shared memory in step 308, and the process of microcomputer.n is terminated. If the failure detection flag has been set in step 303, the processing immediately proceeds to step 307 because it is not necessary to perform the processing immediately after the failure detection (step 304 to step 306).
[0042]
On the other hand, if the failure detection signal of the microcomputer .n + 1 is not input in step 302, the process proceeds to step 309 to determine the failure detection flag. If the failure detection flag has been set in step 309, it is determined that the microcomputer .n + 1 has failed so far (that is, recovery from failure), and the failure detection flag is reset in step 310. If the microcomputer .n + 1 is out of order, the sampling cycle that has been changed in accordance with the increase in processing load is returned to the normal state in step 311 and the processing is terminated. If the failure detection flag is reset in step 309, the microcomputer .n + 1 is operating normally, and the process is terminated.
[0043]
In this embodiment, since only one individual bus is accessed during normal operation of the microcomputer, no bus contention occurs between the two individual buses of each microcomputer, and no bus arbitration circuit is required in the individual bus interface circuit. This has the effect of simplifying the hardware. In addition, there is an effect that the efficiency can be improved because the operation rate of the microcomputer is not lowered due to bus competition in the individual bus. Further, when a normal microcomputer burdens the processing of the failed microcomputer, the sampling period is changed in accordance with the increase in processing time accompanying the increase in the burden, so that the system can be operated stably.
[0044]
Next, an embodiment of the mutual monitoring method by software between the arithmetic units in the above embodiment and the diagnosis method of the shared bus and the individual bus will be described with reference to the configuration diagram shown in FIG. 6 and the flowchart of FIG. 6 that have the same reference numerals as those in FIG. 1 have the same functions.
[0045]
In this embodiment, the diagnosis is performed by comparing and determining the diagnosis data of the shared bus and the diagnosis data of the individual bus. Therefore, information communication means on the shared bus and information communication means for each individual bus are required. In the configuration of FIG. 6, the shared memory 5 is used as the communication means on the shared bus, and the communication means between the two arithmetic units. This is performed using the individual memories 6.1 to 6.n connected to each individual bus. From this, the calculating part n performs a mutual diagnosis with the two calculating parts of the calculating part n-1 and the calculating part n + 1.
[0046]
The processing contents of the microcomputer .n when the microcomputer is used as the calculation unit will be described below with reference to the flowchart of FIG. As described above, the microcomputer .n performs the mutual diagnosis with the two microcomputers of the microcomputer .n-1 and the microcomputer .n + 1. However, since the processing contents are the same, only the microcomputer .n-1 is shown in FIG. explain. In this embodiment, each microcomputer outputs the same data according to a predetermined rule as diagnostic data to the shared memory and the individual memory as (CD.n-1) and (LD.n-1).
[0047]
As processing contents of the microcomputer n, first, the diagnosis data (CD.n-1) output from the microcomputer n-1 in step 400 is taken from the shared memory, and then the diagnosis output from the microcomputer n-1 in step 401. Data (LD.n-1) is taken in and it is determined in step 402 whether the two values (CD.n-1) and (LD.n-1) are equal.
[0048]
If it is determined in step 402 that the two values are equal, it is determined that both the shared bus and the individual bus are normal, and the process proceeds to step 403 to execute the process of the microcomputer .n at the normal time. Thereafter, in step 404, the same value is output to the shared memory and the individual memory as diagnostic data of the microcomputer .n itself, and the process is terminated.
[0049]
On the other hand, if it is determined in step 402 that the two values are not equal, the process at the time of abnormality from step 405 is executed. In step 405, the validity of whether the data (CD.n-1) on the shared memory side conforms to the above-mentioned certain rule is checked. If it is correct, the data on the individual bus side is incorrect. Therefore, it is assumed that the individual bus .n-1 is out of order and the process proceeds to step 406.
[0050]
In step 406, the individual bus .n-1 determined to be faulty is disconnected from the microcomputer .n, and then in step 407, the processing of the microcomputer .n when the individual bus .n-1 fails is executed. In addition, after the data communicated on the failed individual bus .n-1 is exchanged using the shared bus in step 408, the diagnosis data is output only to the shared memory in step 409, and the individual bus is output. The processing at the time of failure of .n−1 is terminated.
[0051]
If the value of (CD.n-1) is an invalid value in step 405, the process proceeds to step 410, and the diagnostic data (LD.n-1) on the individual memory side is set as described above. Check validity as well. If the diagnostic data (LD.n-1) is correct in step 410, it is determined that the shared bus is faulty because the data on the shared bus side is incorrect, and the process proceeds to step 411.
[0052]
In step 411, after the computation processing of the microcomputer .n when the shared bus fails, the data communicated by the shared bus in step 412 is communicated on behalf of the individual bus .n-1 and the individual bus .n. I do. Thereafter, in step 413, the diagnosis data of the microcomputer .n is output only to the individual memory, and the processing at the time of the shared bus failure is terminated.
[0053]
If the diagnosis data (LD.n-1) is incorrect in step 410, the microcomputer .n-1 itself is out of order because both the data on the shared bus side and the individual bus side are incorrect. It judges that it is a thing and moves to step 414. In Step 414, after the microcomputer .n-1 is disconnected from each bus so that the microcomputer .n-1 does not output an error signal to the shared bus and the individual bus, in Step 415, the microcomputer .n-1 is failed. .n is executed. Finally, in step 416, the same value is output to the shared memory and the individual memory as diagnostic data with other normal microcomputers, and the process ends.
[0054]
In this embodiment, it is possible to use a method for avoiding a deviation in the timing of delivery of diagnostic data with other microcomputers by providing a method for confirming diagnostic data several times, a flag for completion of transmission / reception with a memory, etc. is there. Further, the detected failure location can be stored and displayed, and the processing can be simplified without duplicating the processing for determining the failure location at the time of failure by storing the failure.
[0055]
In this embodiment, diagnostic data is communicated between a plurality of arithmetic units through a shared bus and a specific bus, and the diagnostic data is compared and discriminated, thereby allowing mutual monitoring of each arithmetic unit for failure and the like and two buses. Since each of the above can be simultaneously monitored by software and can be backed up against any failure of the arithmetic unit or the bus, non-stop operation is possible and the reliability of the system can be improved. In addition, when an information communication means is provided for each individual bus, information used only by two arithmetic units coupled by the individual bus can be communicated without using the shared bus, so the amount of data on the shared bus is reduced. As a result, the operating rate of each computing unit can be improved and the performance of the system can be improved. Furthermore, there is an effect that maintenance is facilitated by determining the cause of the failure when the failure occurs and displaying the failure location.
[0056]
Next, another embodiment of the network system using the present invention will be described with reference to FIG. In FIG. 8, the same reference numerals as those in FIG. 1 have the same functions. In this embodiment, the configurations of the two individual buses included in each of the arithmetic units 7.1 to 7.n and the input / output circuit (I / O) connected to each individual bus are the same as those in FIG. In the following, a configuration method of the shared bus and the shared bus interface of each of the arithmetic units 7.1 to 7.n will be described.
[0057]
The arithmetic unit 7.n includes two shared bus buffers 10.n1 and 10.n2 as a shared bus interface. The two shared bus buffers are interconnected in the arithmetic unit 7.n, and the arithmetic unit It is also connected to the 7.n internal bus via the internal buffer 10.n3. As in the configuration of FIG. 1, the internal buffer 10.n3 includes an arbitration circuit that does not cause bus contention in the shared buses 2.1 to 2.n. Of these two shared bus buffers, one shared bus buffer is connected to one shared bus buffer of another computing unit, and the other shared bus buffer is one shared bus of another other computing unit. Connect to the buffer. That is, the shared bus is connected in series between the respective arithmetic units by a plurality of shared buses 2.1 to 2.n in the same manner as the connection method of the individual buses. When this system is operating normally, the two shared bus buffers in each arithmetic unit are both in an operating state, so that each arithmetic unit has a plurality of shared buses 2.1 to 2.n as one bus. It becomes a system similar to FIG.
[0058]
In this configuration, when a failure occurs in the arithmetic unit 7.n, the two shared bus buffers 10.n1 and 10.n2 remain in the operating state, and only the internal buffer 10.n3 is set in the non-operating state. As a result, only the failed arithmetic unit can be separated from the shared bus without affecting other normal arithmetic units. Further, when any one of the plurality of shared buses 2.1 to 2.n fails, for example, when the shared bus 2.1 fails, only the failed bus is separated. That is, only the failed shared bus 2.1 is separated by disabling the shared bus buffers 10.12 and 10.21 connected to the failed shared bus 2.1. Here, using the individual bus 3.1 connecting the same arithmetic units as the shared bus 2.1, the two arithmetic units bear the transfer processing, thereby enabling the backup of the faulty shared bus 2.1. Operation can be continued without stopping the system.
[0059]
According to the present embodiment, since the shared bus can be separated between the arithmetic units, the failure range can be suppressed to a narrow range without the influence of the shared bus failure affecting all the arithmetic units. effective. In addition, since the shared bus other than the failure can be operated in the same manner as normal, there is an effect that a decrease in system performance is reduced. Furthermore, maintenance work such as repair or replacement of a faulty bus does not affect other shared buses, so that maintenance efficiency can be improved.
[0060]
Next, another embodiment of the network system using the present invention will be described with reference to FIG. 9, the same reference numerals as those in FIG. 1 have the same functions. In this embodiment, the network system shown in FIG. 1 has a hierarchical structure. In other words, a plurality of lower arithmetic units 11.1 to 11.n are connected to the individual bus 3.1 shared only by the upper arithmetic units 1.1 and 1.2 in FIG. For .1 to 11.n, the individual bus 3.1 is handled as a shared bus.
[0061]
In addition, each of the arithmetic units 11.1 to 11.n has two individual bus interfaces similar to the upper arithmetic units 1.1 and 1.2, and each individual bus interface has a plurality of individual buses 31.0. Coupled in series at ~ 31.n. Further, the lower arithmetic units 11.1 to 11.n connect input / output circuits (I / O) 40.0 to 40.n necessary for control arithmetic processing to the individual buses 31.0 to 31.n. Build a hierarchical network system.
[0062]
In this embodiment, only the lower arithmetic units 11.1 to 11.n are connected to the individual bus 3.1. However, an input / output circuit unique to the upper arithmetic units 1.1 and 1.2, Alternatively, a common input / output circuit can be connected to the lower arithmetic units 11.1 to 11.n connected to the individual bus 3.1. Further, in the present embodiment, a network system having two hierarchies of arithmetic units is shown, but an n (n is an integer greater than 2) hierarchy corresponding to the target system can be realized with the same configuration. Furthermore, by making the specifications of the shared bus and the individual bus in each hierarchy the same, it is possible to share the arithmetic units and input / output circuits in each hierarchy. It is obvious that the above-described backup method for the failure of the arithmetic unit or the bus is also applied to the hierarchically structured network system shown in the present embodiment.
[0063]
According to the present embodiment, by hierarchizing the network system to be controlled, the number of hierarchies can be freely changed according to the target system, and the operation unit of each hierarchy can be realized on an optimum scale. In addition, by unifying the bus specifications at each layer, there is an effect that the arithmetic unit or the input / output circuit at each layer can be standardized.
[0064]
Next, another embodiment of the network system using the present invention will be described with reference to FIG. In the other individual buses or input / output circuits shown in FIG. 10, the same reference numerals as those in FIG. In the present embodiment, in a system having a plurality of horizontal distributed network systems shown in FIG. 1, a plurality of horizontal distributed network systems are connected by connecting the arithmetic units of each horizontal distributed network system with a third individual bus. Communicate information between them.
[0065]
That is, the arithmetic units 1.1 and 1.2 (or 1.1 ′ and 1.2 ′) of the two horizontally distributed network systems in FIG. 10 are connected in series between the arithmetic units in the network. In addition to the three individual bus interfaces, a third individual bus interface is newly provided. Then, a third individual bus 3.01 (or between the third interface of the calculation unit 1.1 (or 1.2) and the third interface of the calculation unit 1.1 ′ (or 1.2 ′) is connected. Alternatively, the information communication between the two horizontally distributed network systems is performed by coupling in 3.12).
[0066]
Therefore, as a system configuration, two horizontally distributed network systems are symmetrically coupled by individual buses. In this embodiment, all the arithmetic units have three individual bus circuits and are connected to each other's networks, but only the arithmetic units that require information communication between the networks are connected by the third individual bus. It is also possible to adopt a configuration. Further, an input / output circuit can be connected to the third individual bus.
[0067]
According to the present embodiment, in information communication between a plurality of network systems, it is possible to perform direct communication or resource sharing between operation units that require information, which is unnecessary for other operation units. Since there is no need to communicate data via a shared bus, the speed of information communication can be increased, the utilization rate of the shared bus can be suppressed, the operating rate of each computing unit can be improved, and the operating efficiency of each network can be improved. There is.
[0068]
Next, another embodiment of the network system using the present invention will be described with reference to FIG. In FIG. 11, the same reference numerals as those in FIG. 1 have the same functions. The two individual bus interfaces of the two arithmetic units 1.1 and 1.2 are directly connected by the two individual buses 3.1 and 3.2, thereby duplicating the individual buses. Input / output circuits 40.a to 40.n and 41.a to 41.n are connected to each of the duplexed individual buses 3.1 and 3.2.
[0069]
Each of these input / output circuits is input to the switches 9.1 to 9.n, and an input / output circuit having the same function is connected to one switch from different individual buses (for example, the switches 9.n and Input / output 40.n and 41.n to be connected have the same function). In other words, each switch selects either one of the input / output circuits. Even if one of the arithmetic units, individual buses, or input / output circuits fails, the side that is connected to the normal function is selected. By selecting, the processing of the target system can be executed without stopping the system. Accordingly, the processing contents executed by the arithmetic units 1.1 and 1.2 execute the same arithmetic processing for each input / output circuit.
[0070]
In addition, as a switching method of the switching device in the present embodiment, hardware switching by a failure signal (however, it is defined as one of the normal times), or from an arithmetic unit to which both individual buses are connected By switching by the command of. Further, it is obvious that the individual bus acquisition method of the arithmetic unit can be realized by either the configuration of FIG. 2 or FIG. Furthermore, although the input / output circuit is duplexed, the input / output that does not need to be duplexed may be connected independently.
[0071]
According to the present embodiment, the individual bus and the input / output circuit can be duplicated without changing the configuration of the arithmetic unit having one shared bus and two individual buses. However, there is an effect that a highly reliable system without stopping the target system can be easily realized.
[0072]
Next, as an example of applying the above-described network system or multiprocessor system, ten examples corresponding to the configuration of FIG. 1 which is the basis of the present invention are shown in Table 1, and each application example will be described below. .
[0073]
[Table 1]

[0074]
First, No. 1 in Table 1 is one in which the present invention is applied to information control of railway lines in a railway transportation system. The information processing equipment of the main station (or control room) that is the core of the target route is connected to a shared bus across the entire route to communicate operation information and the like. In addition, each nuclear station is connected with an individual bus, and local stations, traffic lights, and circuit breakers that exist between the nuclear stations are set as I / Os connected to the individual bus. Is to do. In addition, by connecting an information terminal device or the like as an input / output device connected to an individual bus, it can be applied as an information communication network such as a seat reservation system.
[0075]
In this application example, information can be communicated via a plurality of individual buses even in the case of a shared bus failure across the entire route, and connected to the failure of an information processing device at the nuclear station via an individual bus. In addition, since the information processing device at another nuclear station can be backed up, there is an effect that continuous operation is possible without stopping the system even if the bus and the information processing device fail.
[0076]
Next, No. 2 in Table 1 is an example in which the present invention is applied to an in-vehicle control device for a railway vehicle, and FIG. 12 shows a detailed application example. The number of connected vehicles is n, and the control device for each vehicle is connected by a common bus 2 common to all vehicles, and the vehicle control units 11.1 to 11.n provided in each vehicle are connected to a plurality of individual buses. It binds with 3.1 to 3.n. The equipment connected to each individual bus varies depending on the vehicle, but there are subordinate control units such as door control, air conditioner control, lighting control, and drive motor control device. A vehicle speed command, a temperature setting value for each vehicle, and the like are communicated to the shared bus 2, and a control device in each vehicle executes processing according to each command value.
[0077]
In FIG. 12, by connecting the individual bus 3.n of the last vehicle and the individual bus 3.0 of the first vehicle, all devices connected to each individual bus can be controlled from two vehicle control units, It is possible to continue the operation even if the vehicle control unit fails. The information transmitted through the shared bus can also be used as an in-car service such as a radio line or a telephone line. In this application, each vehicle control unit manages all the lower level control units in the vehicle, but it is clear that the sharing method can be freely set, such as sharing the lower level control units in other vehicles. is there.
[0078]
No. 3 in Table 1 is an example in which the present invention is applied to a plurality of rolling stand controls in a steel rolling facility. A control device installed in each of the plurality of rolling stands is coupled by a shared bus, and a rolling roll driving device and a reduction driving device for controlling each rolling stand are connected to each individual bus. Various command values such as the roll speed and rolling speed of each rolling stand, or information such as the operating status of each rolling stand are communicated to the shared bus 2 that spans all rolling stands, and cooperative control among a plurality of rolling stands is realized. it can.
[0079]
In this application example, among the control devices for a plurality of rolling stands, in addition to being able to back up when one control device fails, detailed information communication between two rolling stands can be performed by an individual bus, There is an effect that cooperative control between the rolling stands is facilitated.
[0080]
No. 4 in Table 1 is an example in which the present invention is applied to a rolling mill higher than the above-mentioned No. 3 in the steelworks. Control units provided in various facilities such as a heating furnace and a rolling mill in the steelworks are connected by a shared bus, and information such as operation commands and operation status of each facility in the steelworks is communicated. The individual buses connecting the facilities are connected to a lower level control device in each facility, for example, a temperature control device of a heating furnace, a plate thickness control device or a tension control device of a rolling mill. By connecting the No. 3 system to the individual bus shown in this example as a shared bus for the rolling equipment shown in No. 3 above, the No. 4 system becomes the upper level and the No. 3 system becomes the lower level. The rolling mill control system in the steel works can be constructed in a system having a hierarchical structure shown in FIG.
[0081]
No. 5 in Table 1 is an example in which the present invention is applied to facilities of a thermal power plant. Control units provided in various facilities such as a boiler and a turbine in a thermal power plant are connected by a shared bus, and information such as an operation command and an operation status for each facility in the power plant is communicated. The individual buses connecting the facilities are connected to lower-level control devices in the facilities, for example, a steam pressure control device or a temperature control device for a boiler, or a turbine pressure control device for a turbine.
[0082]
No. 6 in Table 1 describes a bank online system as an example in which the present invention is applied to a wide-area computer network system. All of the computers installed in the head office and each branch of the bank are connected by a shared bus, and the individual bus connects the branches (or between the head office and the branch) that are close to each other. The individual bus is connected to an online CD terminal or window terminal installed at the head office or branch, or a terminal device at a branch office under the jurisdiction of the head office or branch.
[0083]
Therefore, each terminal can be managed by two computers, a shared bus is used for nationwide information communication, and an individual bus is used for information communication in a relatively small area in a specific area. This has the effect of providing high-speed services to customers.
[0084]
No. 7 in Table 1 describes a network of a building OA system as an example in which the present invention is applied to a computer network system in a narrow range. A host computer that manages the total system in the house and a network controller installed on each floor are connected to the shared bus. The individual buses output from these network controllers are wired to each floor and connected to other upper and lower network controllers. Accordingly, OA devices such as workstations, personal computers, and printers installed on each floor can be managed from the network controllers on the two floors, so that each OA device can continue to operate even if the network controller fails. It becomes composition.
[0085]
No. 8 in Table 1 describes a system applied to a motor control device as a device control device using a multiprocessor to which the present invention is applied. FIG. 13 shows a specific example of the printed circuit board of the control unit or the bus wiring method in the control device. As the calculation unit of the motor control device in this example, a multiprocessor system using a microcomputer is configured for each control block such as speed control and current control, and one calculation circuit or one input / output circuit for each function is provided. It is realized with the printed circuit board. Input / output circuits connected to individual buses include analog signal processing circuits such as current detection circuits, encoder pulse processing circuits, or PWM pulse output circuits to power converters. Each printed circuit board is controlled. Connected to an individual bus corresponding to the microcomputer that executes As an example of a method of mounting these printed circuit boards on the control unit, it can be configured as shown in FIG. Although FIG. 13 shows a configuration that can be extended to a plurality of control units, it is also possible to use a single unit.
[0086]
In FIG. 13, two control units 50 and 60 each have printed circuit boards (hereinafter referred to as microcomputer boards) 51 to 53 and 61 to 63 each including three microcomputers, and an input / output circuit printed therebetween. Circuit boards 511-532, 611-632 are arranged and connected by a backboard. The back board to which each printed circuit board described above is connected in each control unit is wired with a shared bus at the top and a plurality of individual buses at the bottom with staggered wiring for each microcomputer board. The board and the input / output circuit are connected to one shared bus and two individual buses.
[0087]
By adopting such a mounting method, each individual bus and input / output circuit are shared by two adjacent microcomputer boards, and the configuration of the present invention can be realized. It should be noted that when a common input / output circuit is connected to all the microcomputer boards, it is obvious that a shared bus interface is provided in the input / output circuit and connected to the backboard. A method of extending to another control unit is realized by connecting expansion buses output from the expansion units 55 and 65 including drivers and receivers. That is, by connecting CA1, CB1 and CA2 and CB2 which are expansion bus ports of the shared bus, and LA1, LB1 and LA2 and LB2 which are expansion buses of individual buses, the control units are connected in series, respectively. Expansion of 2 units or more is possible. In addition, when the number of expansion of the control unit is limited to two units, one port is sufficient for the expansion bus of the shared bus and each is directly connected to each other, and the individual bus connects LA1 and LB2, LB1 and LA2 of the two expansion ports. Since all the microcomputer boards are connected in a ring shape by coupling, each input / output circuit is managed by two microcomputers.
[0088]
In this application example, the motor control device is described. However, the present invention can also be applied to various control devices to which a multiprocessor system is applied, such as a power electronics control device such as a power converter. Further, when the back board is configured so that two individual buses are wired in parallel between the two microcomputer boards, the control device in which the individual buses and the input / output circuits as shown in FIG. 11 are also duplicated. Can be realized with a microcomputer board of the same specification.
[0089]
No. 9 in Table 1 is an example in which the present invention is applied to a road traffic system that monitors or controls the amount of automobile traffic on the road. A computing unit is placed at the main intersection on the road, and traffic lights, traffic monitoring devices, etc. are installed on the individual buses connecting the main intersections. Traffic volume from traffic monitoring devices installed at each point, or traffic signal operation information, etc. are transmitted over a shared bus, and each arithmetic unit controls traffic volume by operating traffic signals, allowing smooth traffic with less traffic congestion. Can be realized.
[0090]
No. 10 in Table 1 describes an example in which the present invention is applied to a power network system, particularly to a home power supply system. The plurality of distribution stations are supplied with power from a common power bus, and supply power to each home from a branch line connecting the distribution stations. That is, a plurality of pole transformers are installed on the branch line, and a predetermined voltage is supplied from the pole transformer to each home.
[0091]
Therefore, each branch line can construct an electric power network system that can supply electric power from two distribution stations, and can prevent a power outage to each household even if the distribution station fails. In addition, there are three branch lines output from the distribution station, and one of them is connected to a distribution station of another power network system, that is, a plurality of power network systems are combined as shown in FIG. Even when a power bus of one power network system fails, it is possible to realize a power network system that can continue to supply power from a power bus of another power network system via a distribution station.
[0092]
【The invention's effect】
According to the present invention, in a network system having a plurality of control operation functions, a double bus configuration having a shared bus and an individual bus, and by connecting an input / output circuit unique to each control operation function to the individual bus, Enables a high-speed system with less contention on the bus, and each individual bus is connected and shared with two control operation functions, so one of the input / output circuits connected to each individual bus has a failure in one control operation function In this case, it is also possible to access from the other control operation function, so that even if the control operation function fails, the normal control operation function connected to the individual bus can take over the control processing of the failed control operation function. This makes it possible to operate the system without stopping with minimal configuration without multiplexing or redundancy even if there is a malfunction in the control operation function, thus building a highly reliable system. There is an effect that kill.
[0093]
In addition, the control operation function has two individual bus interfaces, and each individual bus interface is connected in series with other different control operation units, so that the configuration of all control operation units can be standardized according to the system scale There is an effect that the control calculation function can be easily expanded.
[0094]
In addition, since each individual bus can be accessed only with two control calculation functions, even when the system scale increases and the number of control calculation functions increases, the decrease in processing capacity of each control calculation function is suppressed. It is possible to realize a high-performance system.
[0095]
Furthermore, by performing diagnosis data output and discrimination using two systems of information communication means of shared bus and individual bus, mutual diagnosis of arithmetic units and fault diagnosis of shared bus or individual bus can be realized by software. Since the operation unit or bus can be backed up by another operation unit or bus, a highly reliable system can be constructed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment of a network system to which the present invention is applied.
FIG. 2 is a configuration diagram of a calculation unit in FIG. 1;
FIG. 3 is a flowchart for explaining backup processing when the arithmetic unit in FIG. 1 is configured in FIG. 2 and the arithmetic unit fails;
4 is a configuration diagram of a calculation unit in FIG. 1. FIG.
FIG. 5 is a flowchart for explaining backup processing when the arithmetic unit in FIG. 1 is configured in FIG. 4 and the arithmetic unit fails.
FIG. 6 is a configuration diagram of a network system according to another embodiment of the present invention.
7 is a flowchart for explaining a diagnosis method in the system of FIG. 6;
FIG. 8 is a configuration diagram of a network system according to another embodiment of the present invention.
FIG. 9 is a configuration diagram of a network system according to another embodiment of the present invention.
FIG. 10 is a configuration diagram of a network system according to another embodiment of the present invention.
FIG. 11 is a configuration diagram of a network system according to another embodiment of the present invention.
FIG. 12 is a detailed configuration diagram when the present invention is applied to the control of a railway vehicle.
FIG. 13 is a specific configuration diagram of a control unit circuit in a control device to which the present invention is applied.
[Explanation of symbols]
1.1 to 1.n: arithmetic unit, 2 ... shared bus, 3.0 to 3.n: individual bus, 40.a to 40.n: input / output circuit used for control arithmetic processing.

Claims (7)

In a system in which target control processing is distributed and executed by a plurality of control arithmetic means, each control arithmetic means includes one shared bus interface means and first and second individual bus interface means. The shared bus interface means is connected to a shared bus that can be commonly used by the plurality of control arithmetic means, and one of the two individual bus interface means is a first individual bus interface means . A bus arbiter for the bus interface , coupled to one individual bus interface means of another specified control operation means by a first individual bus, and the other one second individual bus interface means is a second It has a bus arbiter for the individual bus interface, coupled to the first individual bus control The calculation means to combine the one individual bus interface means of another specified control operation unit in the second individual bus, connected in series to said plurality of control operation unit in a plurality of individual buses, the A bus that is duplicated by a shared bus and a plurality of individual buses, and the control arithmetic means transmits information to the other control arithmetic means connected to the first individual bus via the first individual bus. The other control calculation means can input information to the control calculation means connected to the first individual bus via the first individual bus, and the control calculation means Information can be input to another control arithmetic means connected to the second individual bus via two individual buses, and the other control arithmetic means connected to the second individual bus Information is sent to the control means via the control calculation means. Force is possible, the first individual bus, and the horizontal distributed network system in the second individual bus, characterized in that the input device or output device is connected. "   2. The shared bus according to claim 1, wherein shared storage means for performing information communication between the plurality of control arithmetic means and resources commonly used by the plurality of control arithmetic means are connected to the shared bus, A horizontal distributed network system, characterized in that the bus is connected to peripheral input / output means for performing input / output processing of necessary information individually by the plurality of control arithmetic means or lower control arithmetic means.   3. The storage unit or the information communication unit according to claim 2, wherein a storage unit or an information communication unit is connected to each of the plurality of individual buses together with a peripheral input / output circuit necessary for the plurality of control calculation units for calculation processing. In this case, information used only between two control arithmetic means coupled by the individual bus is stored or information communication is performed, so that the plurality of control arithmetic means are duplicated by the shared bus and the individual bus. A horizontally distributed network system characterized in that information is transmitted through a unified communication path.   The control calculation means according to claim 1 is configured by a device having a calculation function such as a general purpose or dedicated large-scale computer or microcomputer, or a network controller capable of controlling connection and switching of a plurality of networks. Horizontally distributed network system.   In the horizontally distributed network system according to claim 1, when a failure or abnormality of the shared bus is detected by the plurality of arithmetic units, all the shared bus interface units of the plurality of control arithmetic units are made inoperative. When a failure or abnormality of the individual bus is detected, the individual bus interface unit of each of the two control arithmetic units connected to the failed individual bus is deactivated, and the failed shared bus or individual bus is A horizontally distributed network system characterized in that it is separated from the control arithmetic means.   2. The horizontally distributed network system according to claim 1, wherein, when the shared bus fails, information to be transmitted by the shared bus via a plurality of individual buses connected in series with a plurality of control arithmetic means is stored. A horizontal distributed network system characterized in that the control computation process is continued and the control computation processing is continued by backing up information communication for the shared bus failure.   2. The horizontal distributed network system according to claim 1, wherein when the individual bus fails, the two control arithmetic means share information to be transmitted between the two control arithmetic means connected to the failed individual bus. A horizontally distributed network system characterized in that information transmission between the two control arithmetic means connected to the failed individual bus is continued by transmitting the data through the bus.

Images