JP2880375B2 - Multi-bus control method for computer system and computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly reliable computer system, and more particularly to a multi-bus control method and apparatus for a computer system which controls a system bus multiplexed by a plurality of buses.

[0002]

2. Description of the Related Art In a conventional computer system, as disclosed in, for example, Japanese Patent Application Laid-Open No. 62-140155, multiplexing (duplexing) in which a system bus is constituted by a plurality of buses in order to improve the reliability of the system. ) Has been done. In such a duplicated system, a fixed-priority arbitration circuit is provided in the basic processing unit and the input / output processor, and when there is a mismatch in the use request of each of the duplicated system buses, the use of the system bus is permitted. It is known to monitor the response of the basic processing unit and the input / output processor to determine the faulty system and disconnect it.

According to Japanese Patent Laid-Open Publication No. Hei 3-233744, for example, in the multiplexed highly reliable computer system, when an error occurs in an operation system, one of the duplicated channel buses is used for another. There is disclosed a processing system including a redundant central controller and a channel controller that switches to a standby system including a standby channel bus.

Further, according to Japanese Patent Application Laid-Open No. Hei 3-271849, one control unit and a plurality of controlled units are constituted by a request bus and a response bus, which are different from the multiplexed system bus. A multi-bus system is known which is connected by a system bus called a multi-bus and performs centralized monitoring by a multi-bus connection control unit monitoring circuit. In other words, a failure in one controlled unit may cause a failure in one controlled unit due to a poor connection caused by inserting and removing a package constituting the controlled unit to / from a back panel forming a multi-bus. In order to prevent a so-called bus lock failure from spreading, a check circuit is known which determines whether a response signal of a controlled unit is normal or not.

[0005]

In the above-mentioned prior art, the use priority of the multiplexed system bus is fixed, and at the same time, the arbitration circuit is distributed and arranged in each input / output processor. Thus, it was possible to determine the faulty system. However, in the case where the arbitration circuits are centrally arranged in one place and the priority is determined by using round robin, there is a problem that it is not possible to determine a failure system according to the related art.

According to Japanese Patent Application Laid-Open No. Hei 3-233744, when an error occurs in an operation system in a processing system including a duplicated central control device and a channel control device, switching to a standby system route is performed. Test the backup route by checking the signal level for trouble-free operation.
It does not teach any method of detecting an abnormality of a device connected to the system bus and giving priority to using the system bus.

Further, a system in which a system bus called a multi-bus composed of a request bus and a response bus, which is known from Japanese Patent Application Laid-Open No. Hei 3-271849, is centrally monitored by a multi-bus connection control unit monitoring circuit is known as a system. The multiplexing of the system bus for high reliability is different in its technical meaning, and the controlled unit is selected by a selector, but the conditions for disconnection are also different, and devices connected to the system bus are different. It does not teach how to detect abnormalities in the system and give priority to using the system bus.

Accordingly, an object of the present invention is to provide a multiplexing system in which the operation of the system can be continued when the priorities of the multiplexed system buses are determined using round robin. It is possible to determine which of the systems is to be disconnected, and to provide a multi-bus control method for a computer system and a device therefor, which enable detection of a faulty part. Here, the round robin is a method of determining the priority of the second priority in the next priority.

[0009]

According to the present invention, there is provided, in accordance with the present invention, a multiplexed system bus, comprising: a basic processing unit connected to the multiplexed system bus; An input / output processing unit connected to a multiplexed system bus, a storage device connected to the multiplexed system bus, and a bus control for controlling arbitration of the multiplexed system bus using a round robin method In a computer system including devices, there has been proposed a multi-bus control method for a computer system in which the bus control device disconnects a system bus based on the number of requests for use of each of the multiplexed system buses.

[0010] It is another object of the present invention to provide a multiplexed system bus, a basic processing unit connected to the multiplexed system bus, and an input processing unit connected to the multiplexed system bus. A computer system comprising: an output processing unit; a storage device connected to the multiplexed system bus; and a bus control device for controlling arbitration of the multiplexed system bus using a round robin method. The control device is achieved by a multi-bus control device of a computer system comprising means for disconnecting the system bus based on the number of requests for use of each of the multiplexed system buses.

[0011]

In other words, according to the method and apparatus for controlling a multi-bus of a computer system according to the present invention, the use of each of the above-mentioned buses can be performed when the number of bus use requests does not match in a multiplexed system bus. By means of the means for separating the system bus based on the number of requests, only some of the system buses are disconnected, but in this case, only the buses with no or few requests are disconnected, so that the system operation can be continued In this way, it is possible to surely disconnect the bus while preventing the failure from spreading to another.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. First, FIG. 2 shows an overall schematic diagram of a high-reliability computer system (FTC) to which a multi-bus control method and a device for a computer system according to the present invention are applied.
In this system, two sets of system bus 1
0-1 and 10-2 are provided, and one or a plurality of basic processing units (BPUs) 11-1, 11-2, 11-3, and 11-4 are provided on these buses.
A bus controller (BC) 1-1 for controlling one system bus (SB) 10-1, a bus controller (BC) 1-2 for controlling the other system bus (SB) 10-2, Further, input / output processors (IOUs) 13-1, 13 to which files and networks are connected
-2 are connected to the system buses 10-1 and 10-2, respectively. A main storage unit (MSU) 12-1 is connected to the system bus 10-1.
2 is connected to another main storage device (MSU) 12-2. In this embodiment, the bus controller (B
C) 1-1, 1-2, main storage unit (MSU) 12-1,
12-2 and input / output processor (IOU) 13-
1 and 13-2 are each used as a set of two units, and each of them uses one set. In this figure, for the sake of easy understanding, each of the redundantly provided components corresponding to the duplicated system buses 10-1 and 10-2 is denoted by A or A in parentheses, respectively. B is displayed (A system, B system). here,
Each device (BPU1-4, MSU12-1, 12-2, I
The bus use requests of the OUs 13-1 and 13-2) are simultaneously sent to the system bus 10-
1 and 10-2. Therefore, in a normal state, when a bus use request exists, the same number of bus use requests exist in the system buses 10-1 and 10-2 (for example, if the number is one, the same number is one). ,
If two, the same number is two). FIG. 3 shows an example of this normal bus use request. Details will be described later.

FIG. 1 shows a bus controller (BC) 1-
1, the internal structure of 1-2 is shown. In the figure, a bus controller (BC) 1-1, 1-2 has a bus use request 2-1 2-2, 2-3, 2-, which is an external signal.
4 to 2 signals, namely, bus use permission 3-1 and 3-
2 arbitration circuits 6-1, 6-2, 6
-3, 6-4 and a comparator 7- which compares the respective output results in order to check the output from these arbitration circuits.
1, 7-2, and further, the bus use requests 2-1 and 2
-2, 2-3, 2-4, a magnitude comparator 5-
1 and 5-2. From the comparison results of these magnitude comparators, two signals, bus disconnections 4-1 and 4
-2 is output.

According to the present invention, the bus use request 2-
When there is a mismatch between 1, 2, 2-2, 2-3, and 2-4, the magnitude comparators 5-1 and 5-2 determine the magnitude of the number of bus use requests, and determine whether the number of bus use requests is small. For disconnecting the bus of the bus, the bus disconnection signal 4-1 (that is,
The system bus 10-1 (system A disconnection) or the bus disconnection signal 4-2 (that is, the system bus 10-2)
By outputting (B system disconnection), it is possible to prevent a failure of one of the system buses from spreading in the system.

FIG. 3 is a time chart of signals of various parts during normal operation. First, from the top of the figure, a basic processing unit (BPU) 11
Next, the waveform of the A-system bus use request 2-1 of A-1 is next to the A of the basic processing unit (BPU) 11-2.
The waveform of the system bus use request 2-2 is shown. Below this, the waveform of the B-system bus use request 2-3 of the basic processing unit (BPU) 11-1 is further displayed.
2 shows the waveform of the B-system bus use request 2-4. As described above, when there is a bus use request, the bus use requests 2-2 and 2-4 are simultaneously sent to the system bus 10.
-1 and 10-2 receive the request, and a bus use request 2-
At the same time, the system buses 10-1 and 10-
2 and that request is met. Therefore, the bus use request 2 in FIG.
In the first half of the timing when -1 and 2-3 and 2-2 and 2-4 exist, the system buses 10-1 and 10-2 are
Two bus use requests 2-1 and 2-2, 2-3 and 2-4 are on board, respectively. On the other hand, in the latter half of the timing (request 2
-2 and 2-4 have disappeared), the request 2-1 is on the system bus 10-1, and the request 2-3 is on the system bus 1
0-2 (that is, one request number). Under such a bus use request, when there is a bus use request from both the basic processing unit (BPU) 11-1 and the basic processing unit (BPU) 11-2, and here, the basic processing unit (BPU) 11 Assuming that the priority of the basic processing unit (BPU) 11-2 is higher than that of the basic processing unit (BPU) 11-1, as shown in the signal waveform of the bus use permission 3 in FIG. BPU) 11-2 (indicated by "2" in the signal waveform in the figure). As a result, the basic processing unit (BPU) 11
-2 outputs a bus use signal 20 having a waveform at the bottom of the figure. After that, bus use permission 3 by round robin
Is a basic processing unit (BPU) 11-
1 (indicated by “1” in the waveform of the bus use permission 3 in the figure), and this basic processing unit (BP
U) 11-1 outputs a bus use signal.

Next, FIG. 4 to FIG.
An example of a case where mismatches occur in -1, 2-2, 2-3, and 2-4, and a time chart of signal waveforms of respective units at that time are shown. First, FIG. 4 shows a case where there is no bus use request 2-4 as a signal (shown by a broken line), that is, a case where only the bus use request 2-4 has no bus use request. In such a case, it cannot be determined which system has failed. However, if one of the systems is not separated, a bus use permission is issued to different devices in the two systems, and different devices use the system bus at the same time.

Therefore, in such a case, in the present invention, the system having less bus use request, in the example shown in FIG. 4, the system B is separated.
That is, as shown in FIG. 5, a bus use request 2- of the A system of the basic processing unit (BPU) 11-2.
2 is turned on by mistake, that is, if there is a so-called ON (ON) failure, a bus use permission 3 which is a permission signal is returned to the failed device, but the bus use signal 20 is not returned from the device. By the round robin, the bus use permission 3 is given to the next device, and in the case of such an ON failure, the processing can be continued without disconnecting the failed A system.

On the other hand, as shown in FIG. 6, the B-system bus use request 2-4 of the basic processing unit (BPU) 11-2 is turned off (OFF) even though it is on. In the case of a so-called OFF (OFF) failure, the bus use permission 3 which is a signal for permitting use of the bus is output to the B system. If the B system is not disconnected, the bus use is permitted to different devices in both systems. And different devices use the system bus at the same time, which causes a failure in the system. In this case, by disconnecting a system having a small number of bus use requests, the operation of the device that actually makes the bus use request is enabled. At the same time, the bus disconnection 4-2, which is a signal for disconnecting the system with a small number of bus use requests, in this case, the system B, is turned on (set to "HIGH").
Thus, the prevention of the spread of the failure is realized.

The operation described above will be described with reference to the flowchart of FIG. 7. In step st1, the bus controller (BC) receives a bus use request, and in the next step st2, the received bus use request is one. To determine if they are As a result, if it is determined that they match (Y), the process proceeds to step 6, where a normal operation, which is an operation process in a normal state, is performed. On the other hand, if it is determined that they do not match (N), the process proceeds to the next step st3, and which of the A system and the B system has a smaller number of bus use requests is determined. As a result, when it is determined that the number of the A system is small (A), the bus of the A system is disconnected as shown in step st4. On the other hand, when the bus use request of the B system is small, as shown in step st5. Then, an operation of disconnecting the B-system bus is performed.

In the embodiment described above, A
It is impossible to determine which of the system or the system B has failed, and which device has failed. Therefore, in the present invention, FIGS. 8 and 9 show a second embodiment in which it is possible to further determine which device of which system has failed.

FIG. 8 shows the internal structure of the two bus controllers (BC) 1-1 and 1-2 in the same manner as in FIG.
1 and 5-2 together with each faulty device storage register 2
1-1 and 21-2 are provided. The faulty device storage registers 21-1 and 21-2 store the magnitude comparator 5
-1 and 5-2, receive signals 22-1 and 22-2 indicating the device numbers for which the bus use requests 2-1 and 2-3 or the bus use requests 2-2 and 2-4 did not match. Bus use signals 20-1 and 20-2 for use permission 3
(Refer to FIG. 5 and FIG. 6). These failure device storage registers 21-1,
By providing 21-2, as shown in Table 1, it is possible to determine which device of which system has failed.

[Table 1]

For example, when the system A is disconnected, when the device whose bus use request 2 does not match uses the bus, the system A is out of order. When the bus is not used, the system B is judged to be out of order. Can be. Also, when the system B is disconnected,
When the device whose bus use request 2 did not match uses the bus, the system B is faulty, and when the bus is not used,
It can be determined that the system A is out of order. These are summarized in Table 1 above, and it is clear that it is possible to determine which device of which system has a fault by using the faulty device storage registers 21-1 and 21-2. It is.

The details of the above operation will be described with reference to the flowchart of FIG. This flowchart is for judging a faulty device in addition to the flowchart shown in FIG. 7, and steps st1 to st6 are the same as those in FIG. 7, and description thereof is omitted here.
In this flowchart, the disconnection of the bus (s
After performing t4 and st5), steps st7 and st5
In step 8, each device determines whether or not a bus use signal 20 (see FIGS. 5 and 6) has been returned from the device whose bus use request did not match, thereby determining a failure system. Specifically, A
If a bus use signal is returned from the device whose bus use request did not match when the system was disconnected, it is determined that the system A is faulty (step st9), and if the bus use signal is not returned, the system B is faulty. A decision is made (step st10). Also,
If the bus use request returns from the device whose bus use request did not match when the system B was disconnected, the system B is determined to have failed (step st10).
It is determined that the system has failed (step st9).

[0024]

As is apparent from the above detailed description, according to the multi-bus control method and apparatus of the computer system of the present invention, even in the centralized round-robin arbitration circuit, the use request of the system bus is required. In the case of inconsistency, one of the systems is reliably disconnected, preventing the spread of failures and enabling the continuation of system processing. It has the effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a detailed structure of an apparatus for implementing a multi-bus control method for a computer system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of a computer system according to the embodiment of the present invention.

FIG. 3 is an output waveform diagram of each unit for explaining the operation of the multi-bus control device when the system bus is normal.

FIG. 4 is an explanatory diagram illustrating an operation of the multi-bus control device when a system bus fails.

FIG. 5 is an output waveform diagram of each section for explaining the operation of the multi-bus control device when an ON failure occurs in the system bus.

FIG. 6 is an output waveform diagram of each section for explaining the operation of the multi-bus control device at the time of an off failure of the system bus.

FIG. 7 is a flowchart for explaining the operation of the multi-bus control device.

FIG. 8 is a block diagram showing a configuration of a multi-bus control device according to another embodiment of the present invention.

FIG. 9 is a flowchart illustrating an operation of the multi-bus control device according to the other embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Bus controller 2 Bus use request signal 3 Bus use permission signal 4 Bus disconnection signal 5 Large / small comparator 6 Arbitration circuit 7 Comparator 10 System bus 11 Basic processing unit 12 Main storage device 13 Input / output processor 20 Bus use signal 21 Fault device storage Register 22 Bus use request mismatch signal

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroaki Fukumaru 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant, Hitachi, Ltd. (72) Yoshihiro Miyazaki 5-2-2 Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Inside the Omika Plant of Hitachi, Ltd. (56) References JP-A-62-140155 (JP, A) JP-A-2-254543 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB G06F 13/00 G06F 11/20 G06F 13/36

Claims (6)

(57) [Claims] 1. A basic processing unit,
When a bus use request is generated from each device connected to the input / output processing unit, the storage device, and each of these devices, each system bus receives the use request for each of the bus use requests. And a bus controller that controls the adjustment of the multiplexed system bus using a round-robin method. In the computer system, the bus controller is configured to control each of the multiplexed system buses. A multi-bus control method for a computer system, comprising comparing the number of bus use requests and separating a system bus having a small use request number. 2. A basic processing unit,
When a bus use request is generated from each device connected to the input / output processing unit, the storage device, and each of these devices, each system bus receives the use request for each of the bus use requests. And a bus controller that controls the adjustment of the multiplexed system bus using a round-robin method. In the computer system, the bus controller is configured to control each of the multiplexed system buses. A multi-bus system for a computer system, comprising detecting a mismatch in the number of bus use requests, and disconnecting a system bus based on the number of use requests for each of the multiplexed system buses when the mismatch is detected. Control method. 3. A multi-bus control method for a computer system according to claim 2, wherein after disconnecting said system bus, it is detected whether or not a bus use signal has been received from a device in which a mismatch in the number of bus use requests has been detected. And determining a faulty system of the multiplexed system bus based on the detection result. 4. A basic processing unit,
When a bus use request is generated from each device connected to the input / output processing unit, the storage device, and each of these devices, each system bus receives the use request for each of the bus use requests. And a bus controller that controls the adjustment of the multiplexed system bus using a round-robin method. In the computer system, the bus controller is configured to control each of the multiplexed system buses. A computer system comprising means for disconnecting a system bus based on the number of bus use requests. 5. The bus controller according to claim 4, wherein the bus controller is provided for each of the multiplexed system buses, and each bus controller receives a bus use request from each system bus. A computer system comprising a plurality of arbitration means for arbitration. 6. The device according to claim 5, wherein each of the bus control devices includes a failure device storage register for storing a failure device for each of the multiplexed system buses. Characterized computer system.