JP2630100B2 - Fault handling method for interprocessor communication bus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault handling system for an interprocessor communication bus in a multiprocessor type switch having a plurality of processors connected by a bus system.

[0002]

2. Description of the Related Art Conventionally, in this type of fault handling system for an inter-processor communication bus, diagnosis is performed for all of a plurality of processors or bus cables which are constituent elements and a bus control device for controlling the inter-processor communication bus. Otherwise, the faulty device cannot be identified.

However, since the duplicated processors are unified during the execution of the diagnosis, if the diagnosis of all the processors is executed, the diagnosis processing time is long and the safety factor of the system is reduced. Even if the cause is a failed processor, it is common to disconnect the failed processor or the bus itself.

[0004]

As described above, in the conventional fault handling method for the inter-processor communication bus, any of the constituent processors or bus cables connected to the bus system and the bus controller has a fault. Even so, there is a drawback that since the device that has detected the failure is disconnected, maintenance personnel are required to identify the cause.

[0005] In addition, even if a failure occurs in the processor, if the failure is detected by the bus control device, the communication bus is disconnected.

[0006]

According to the present invention, there is provided a multiprocessor system having a plurality of processors connected by a bus system. Occurs, the processors that have transferred information at the time of occurrence of this failure and the processors connected to both ends of the bus system are set as the processors to be diagnosed, and automatic diagnosis of each processor is sequentially performed to search for the cause, In this configuration, only the processor determined as a failure among the processors to be diagnosed is automatically separated from the system configuration of the system.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the flow of a program in the failure processing according to one embodiment of the present invention, and FIG. 2 is a diagram showing an example of the configuration of an exchange system for explaining one embodiment of the present invention. In FIG. 2, each of the duplicated processors 1 to 1
8 (here, a multi-system with eight processors) is connected in a bus manner by redundant communication buses 9 and 10 and is controlled by bus controllers 11 and 12. Hereinafter, a case where the processor 3 performs communication with the processor 5 will be described as an example.

The processor 3 issues an inter-processor communication request to the communication bus 9. The bus control devices 11 and 12
After knowing that the processor 3 is making a communication request and instructing another processor to wait, the processor 3
To the transfer. The processor 3 sets the address signal of the partner processor 5 on the communication bus 9 and executes the transfer. The partner processor 5 receives the transfer information and reports normal termination to the transmission source processor 3. The transmission source processor 3 ends the communication processing upon receiving the report. The bus controllers 11 and 12 instruct the other processors to cancel the wait after the transfer of the processor 3 is completed.

FIG. 3 is a diagram showing details of the processor 3 and the processor 5 extracted from FIG. Each processor and the bus control device described in FIG. 2 are controlled by a redundant configuration of the 0 system and the 1 system as shown in FIG. Further, each processor controls communication of the bus by a transmission and reception circuit. The failure processing will be described below with reference to FIGS. 1 to 6. At this time, it is assumed that the system 0 is used in all the bus control devices and processors. Therefore, all of the first systems are standbys in a duplex configuration.

When a communication failure is detected in the processor 3 on the transmission side due to the transmission and reception circuit 5f of the processor 5 on the other side during the processing described in FIG. 2, a failure processing program is started and shown in FIG. So the sending processor 3
The system 0 is disconnected from the system, and the communication processing is resumed in the system 1 (step 1; S1). In this case, assuming that the partner processor 5 has the cause of the failure, the failure occurs again. However, this time, the processor 3 on the transmission side performs the single-system operation, and the failure processing program is as shown in FIG. After disconnecting the communication bus 9 as shown, the communication bus 10 is used. This allows the processor 5 to operate normally because of the use of the transmission and reception circuit 5e. In this case, the 0 system of the processor 5, which is the true cause, cannot detect the failure.

However, in the processing of the present invention, after being separated as shown in FIG. 4 by the failure processing program, a failure search program is started and, as shown in FIG. The information in the area is searched, and all the processors that have performed the information transfer at the time of the failure are set in the processor information area to be diagnosed (S2). In addition, the first and last processors connected in a bus manner are simultaneously set in the processor area to be diagnosed in consideration of a trouble such as a communication bus cable.

Thereafter, the communication bus 9 is disconnected as shown in FIG. 5, and the bus controllers 11 and 12 are automatically diagnosed using the communication bus 9 (S3). If the result is normal, the diagnosis is performed by the automatic diagnosis program for all the processors set in the diagnosis target processor area for the system used before the occurrence of the failure (S4). In the case of this example, the communicating processors 3 and 5 and the first and last processors 1 and 8 of the communication bus are to be diagnosed, and the diagnosis is sequentially performed.

As a result of the automatic diagnosis program, the processor 5
Since a diagnosis error occurs in the 0-system bus test, the 0-system of the processor 5 is disconnected, and then the other devices are returned to the duplex operation (S5). Then, as shown in FIG. 6, the system 0 of the processor 5, which is the true cause, is automatically separated from the system.

As described above, since the diagnosis is performed by narrowing down the devices to be diagnosed, there is an effect that the diagnosis time can be shortened in a system having more processors.

[0016]

As described above, according to the present invention, the diagnosis time can be reduced by narrowing down the target processor, and in the case of a failure in the inter-processor communication bus caused by a specific processor, the communication bus is automatically disconnected without disconnecting the communication bus. By isolating only the faulty system of the specific processor and restarting the system, it is possible to search for the cause of the fault without the intervention of maintenance personnel, thereby improving the stability and maintainability of the system.

[Brief description of the drawings]

FIG. 1 is a diagram showing a flow of a program in failure processing according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of an exchange system for explaining an embodiment of the present invention.

FIG. 3 is a diagram illustrating details of an example of a system configuration in FIG. 2;

FIG. 4 is a configuration diagram of a system in failure processing according to an embodiment of the present invention.

FIG. 5 is a system configuration diagram in a failure process according to an embodiment of the present invention.

FIG. 6 is a system configuration diagram in a failure process according to an embodiment of the present invention.

[Explanation of symbols]

 1-8 processor 9,10 communication bus 11,12 bus controller

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Kumi Mizukami, Inventor 5-7-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation (56) References JP-A-59-219052 (JP, A) JP-A Sho JP-A-64-24650 (JP, A) JP-A-63-227234 (JP, A) JP-A-2-288527 (JP, A) JP-A-59-72255 (JP, A) A) JP-A-60-112155 (JP, A) JP-A-2-306362 (JP, A) JP-A 64-88677 (JP, A)

Claims (1)

(57) [Claims] 1. In a multiprocessor system having a plurality of processors connected by a bus method, when a failure occurs in a communication bus connecting the processors, when a failure occurs, the processors transferring information at the time of the failure and the processors that have transferred information. Processors connected to both ends of the bus system are set as processors to be diagnosed, and automatic diagnosis of each processor is sequentially performed to search for a cause. A fault handling method for an inter-processor communication bus, characterized in that it is separated from the system configuration.