JPH09311841A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the discontinuation of an entire multiprocessor system by cutting the electrical connection between a faulty local bus connected to a faulty slave processor and a system bus if one of plural slave processors in a faulty state. SOLUTION: The fault information is stored in a reset circuit 40-1 where a faulty slave processor 20-1 is connected. Thus, the local buses 70-1 and 80-1 connected to the circuit 40-1 and the slave processors 20-1 and 20-2 connected to the buses 70-1 and 80-1 can be electrically disconnected from the system buses 50 and 60. As a result, the faulty processor 20-1 is separated from a multiprocessor system and the entire discontinuation of this system can be prevented. When the fault of the processor 20-1 is recovered, the fault information on the circuit 40-1 is erased. Then the processor 20-1 is built into the system again.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system which prevents the entire system from being stopped when a slave processor fails.

[0001]

2. Description of the Related Art Conventionally, in a multiprocessor of this type, in order to prevent the entire system from being stopped, when a slave processor fails, access from the master processor is suppressed only to the failed slave processor. It was restarting.

For example, in Japanese Patent Laid-Open No. 3-269759, a master processor requests an error detail notification or an error detail clear notification to a slave processor having a failure at start-up diagnosis. If there is no notification of the above, there is described a configuration for inhibiting access from the master processor to this failed slave processor at the time of restarting.

[0003]

In the above-described conventional multiprocessor system, there may be a cause of failure on the bus to which the failed slave processor is connected. In such a case, the entire system is destroyed. There is a problem that will stop. For example, when a normally operating slave processor is transferring data to and from the memory via the bus, there is a problem that the failed slave processor sends out incorrect data to the bus. This problem occurs because a failed slave processor may not properly recognize the control of the bus usage right by another slave processor.

Further, the master processor recognizes this slave processor as being in a failure state because there is no notification from the slave processor. However, in this case, even if the bus itself fails, the same recognition is performed, so that there is a problem in that even if the slave processor is normal, it is recognized as a failure state.

An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a multiprocessor system capable of preventing the entire system from being stopped.

[0006]

To solve the above problems, a multiprocessor system according to the present invention comprises a master processor, a system bus to which the master processor is connected, a plurality of slave processors, and the plurality of slaves. A plurality of local buses to which at least one of the processors is connected and each of which is connected to the system bus, and an electrical connection between the system bus and the plurality of local buses are connected and connected to the plurality of local buses. If at least one of the plurality of slave processors that has been failed is in a failure state, the electrical connection between the failure local bus to which the failure slave processor is connected and the system bus is cut off. And connecting means.

Further, in another multiprocessor system of the present invention, the connection means includes failure information storage means for storing failure information sent from the failed slave processor, and the failure information is stored in the failure information storage means. It is characterized in that the faulty local bus to which the faulty slave processor is connected and the system bus are electrically disconnected only while the data is stored.

Another multiprocessor system of the present invention includes a system bus, a plurality of local buses electrically connected to the system bus, and a master processor connected to one of the plurality of local buses. Disconnecting electrically disconnecting a faulty local bus connecting a plurality of slave processors connected to the plurality of local buses and a faulty slave processor in the fault state of the plurality of local buses from the system bus Means and
When the master processor is electrically disconnected from the system bus by the disconnecting means, a selecting means for newly selecting a master processor from normal ones of the plurality of slave processors is included.

Further, another multiprocessor system of the present invention further includes local bus acquisition means for obtaining the failed local bus to which the failed slave processor is connected, and the selection means is obtained by the local bus acquisition means. A faulty local bus to which the faulty slave processor is connected. A discriminating unit that discriminates whether or not a master processor is connected to the faulty local bus is included. Is characterized by.

According to another multiprocessor system of the present invention, each of the plurality of slave processors includes a failure processing means for detecting a failure of its own processor and transmitting failure information when the failure is detected. The disconnecting means is provided for each of the plurality of local buses, and electrically disconnects all the processors connected when the failure information is received.

In another multiprocessor system of the present invention, the plurality of slave processors have an identifier, and the selecting means selects a new master processor from the plurality of slave processors based on the identifier. It is characterized by doing.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a multiprocessor system according to a first embodiment of the present invention includes a master processor 10, slave processors 20-1, ...
0-4, reset circuits 40-1 and 40-2, and a main storage device 30. Master processor 10
The main storage device 30 is connected to the system buses 50 and 60.
It is connected to the.

Slave processors 20-1 and 20-
2 is connected to the local buses 70-1 and 80-1,
The local buses 70-1 and 80-1 are reset circuits 4
It is connected to the system buses 50 and 60 via 0-1.

Further, the slave processors 20-3 and 20-4 are connected to the local buses 70-2 and 80-2, and the local buses 70-2 and 80-2 are connected to the system bus 50 and the system bus 50 via the reset circuit 40-2. It is connected to 60.

The bus 50 is connected to the master processor 10, the slave processors 20-1, ..., 20-4 and the main memory device and is used as a data transmission path between them.

The reset circuit 40-1 includes a failure information holding circuit 401-1 which stores failure information when a failure occurs in the slave processors 20-1 and 20-2 connected thereto. This fault information is transmitted from the slave processors 20-1 and 20-2 to the master processor 10
Is sent to the reset circuit 40-1 from the master processor 10. The failure information includes information such as the type of failure and the location where the failure is detected. When the failure information is stored, the reset circuit 40-1 sends a reset signal to the slave processors 20-1 and 20-2 to disconnect the slave processors 20-1 and 20-2 connected thereto from the system bus 50. Is sent.

The reset circuit 40-2 includes a failure information holding circuit 401-2 which stores failure information when a failure occurs in the slave processors 20-3 and 20-4 connected thereto. The fault information is sent from the slave processors 20-3 and 20-4 to the master processor 10, and then the master processor 10 resets the reset circuit 4.
0-2. The failure information includes information such as the type of failure and which part is the failure detected when diagnosing. When the failure information is stored, the reset circuit 40
-2 is the slave processor 20 connected to it
-3 and 20-4 to send a reset signal to the slave processors 20-3 and 20-4 to disconnect from the system bus 50.

Slave processors 20-1, ..., 2
0-4 has diagnostic circuits 201-1, ..., And 201-4, respectively.

The reset circuits 40-1 and 40-2 are
During normal operation, system bus 50 and local bus 70
-1 and 70-2 operate as a connection circuit.

The system bus 60 includes a reset circuit 40-
1 and 40-2 is a transmission line used for sending a reset signal from the main storage device 5.

The local bus 70-1 has one of the slave processors 20-1 and 20-2 connected thereto, the master processor 10 and the main memory 30.
It is used for data transmission to or from either of the above. The local bus 70-1 is connected to the slave processor 20-
It is also used for data transmission between 1 and 20-2. The local bus 70-2 is used for data transmission between one of the slave processors 20-3 and 20-4 connected thereto and one of the master processor 10 and the main storage device 30. In addition, local bus 7
0-2 is also used for data transmission between the slave processors 20-3 and 20-4.

The local bus 80-1 is connected to the reset circuit 4
0-1 to slave processors 20-1 and 20-2
To transmit a reset signal sent to. The local bus 80-2 transmits a reset signal sent from the reset circuit 40-2 to the slave processors 20-3 and 20-4.

Next, the operation of this embodiment will be described.

Referring to FIGS. 1 and 2, at the time of system startup, the master processor 10 instructs the slave processors 20-1, ..., And 20-4 to execute startup diagnostics (steps in FIG. 2). 21). Each of the slave processors 20-1, ..., And 20-4, which has received this instruction, executes the startup process described below. However, only the slave processor 20-1 will be described here and other slaves will be described. The description of the processor is omitted.

Referring to FIGS. 1 and 3, when the slave processor 20-1 receives the start-up diagnosis execution instruction from the master processor 10, the slave processor 20-1 executes the start-up diagnosis (step 31 in FIG. 3). This startup diagnosis is performed by the diagnosis circuit 201-1 of the slave processor 20-1. It is determined whether or not a failure is detected during the start-up diagnosis by the diagnosis circuit 201-1 (step 32 in FIG. 3). When a failure is detected, the failure information is notified to the master processor 10 (step 33 in FIG. 3). Communication between processors is used for notification of failure information. If no failure is detected in step 32, a notification indicating normal is sent to the master processor 10 (step 37 in FIG. 3). After sending the notification that the status is normal, the processing at the start-up is ended and the processing shifts to the normal processing.

Referring to FIGS. 1 and 2, in step 22, the master processor 10 determines whether or not there is a notification from the slave processor 20-1. When there is a notification, it is determined whether or not this notification indicates that a failure has been detected in the slave processor of the notification source (step 23 in FIG. 2). This determination is performed by determining whether or not the notification from the notification source slave processor includes failure information. If the failure information is included, the slave processor 20-1 is instructed to clear the failure in this embodiment based on the content of the failure information (step 24 in FIG. 2). After that, the master processor 10 enters a waiting state in which it waits for the clear end notification from the slave processor 20-1 for a predetermined period. In this waiting state, it is determined whether or not it is within a predetermined period (step 25 in FIG. 2), and if it is within the predetermined period, whether or not there is a clear end notification from the slave processor 20-1. Is determined (step 2 in FIG. 2)
6).

Referring to FIGS. 1 and 3, the slave processor 20-1 determines in step 34 whether or not there is a clear instruction from the master processor 10. If there is a clear instruction, the cause of failure is cleared (step 35 in FIG. 3). When the failure factor can be cleared, the master processor 10 is notified of the completion of clearing (step 36 in FIG. 3). After that, the process at the time of start-up is ended, and the normal operation is started.

Referring to FIGS. 1 and 2, step 2
6, when the master processor 10 receives the clear end notification from the slave processor 20-1, the master processor 10 degenerates the faulty slave processor 20-1 and executes the restart operation (step 2 in FIG. 2).
7). On the other hand, in step 25, when the clear end notification is not received from the slave processor 20-1 within the predetermined time, the failure information is reset circuit 40.
-1 is sent to terminate the startup process (step 28 in FIG. 2).

When there is no notification from the slave processor 20-1 in step 22, the master processor 10 performs the operation of step 28.

Referring to FIG. 1, the failure information is sent to the reset circuit connected to the slave processor in which the failure is detected. The reset circuit 40-1 stores failure information and resets all connected slave processors. The reset circuit 40-1 always maintains all connected slave processors in the reset state while the failure information is stored.

When power is turned on during execution of the restart operation, the reset circuit 40-1 continues to hold fault information. Therefore, the reset circuit 40-1 has local buses 70-1 and 80-. The reset signal continues to be sent to all slave processors 20-1 and 20-2 connected via 1. This keeps slave processors 20-1 and 20-2 separate from the multiprocessor system.

Slave processors 20-1 and 20-
Since 2 is separated, the master processor 10 and
The slave processors 20-3 and 20-4 form a multiprocessor system.

When the failure of the slave processor 20-1 is recovered, the failure information of the reset circuit 40-1 is erased to connect to the reset circuit 40-1 via the local buses 70-1 and 80-1. Reinstall all slave processors 20-1 and 20-2 into the system.

As described above, in this embodiment, the failure information is stored in the reset circuit 40-1 to which the slave processor 20-1 in the fault state is connected, and thereby the failure information is connected to the reset circuit 40-1. Local buses 70-1 and 80-1, and the local buses 70-1 and 80
All slave processors 20-1 and 20-2 connected to -1 can be electrically disconnected from the system buses 50 and 60. Therefore, it is possible to disconnect the failed slave processor from the multiprocessor system and prevent the entire system from being stopped. Furthermore, the local bus 7 is
It is possible to prevent the abnormal data that may have been transmitted on 0-1 from spreading to the entire multiprocessor system.
In addition, the impact on the multiprocessor system can be eliminated if the bus fails.

Next, a second embodiment of the multiprocessor system of the present invention will be described in detail with reference to the drawings.
The second embodiment differs from the first embodiment in that the master processor is connected to the local bus. Other configurations are similar to those of the first embodiment.

Referring to FIG. 4, which illustrates a second embodiment of the present invention, the master processor 10 includes a local bus 70-2.
And 80-2.

The operation of the multiprocessor system of this embodiment is the same as that of the first embodiment up to the point where the cause of failure of the slave processor which has failed is cleared by the instruction of the master processor 10. By this clearing operation, when the failure factor of the failed slave processor cannot be cleared, the failed slave processor is connected to the local bus 70-2 to which the master processor 10 is connected.
And 80-2, or depending on whether the failed slave processor is connected to a local bus different from the local buses 70-2 and 80-2 to which the master processor is connected. different. That is, the operation after the clear processing differs depending on whether the failed slave processor and the master processor 10 are connected to the same local bus or different local buses.

When the failed slave processor and the master processor 10 are connected to the same local bus, the following processing is performed. Master processor 10
Sends fault information to the reset circuit 40-2. As a result, the reset circuit 40-2 is connected to the local bus 70-2.
And the failed slave processor 20-3 and master processor 10 connected via 80-2 are electrically disconnected from the multiprocessor system. By this processing, the master processor 10 is separated from the multiprocessor system, so that a new master processor is selected from the slave processors that are operating normally. This selection is performed by a service processor (not shown). The multiprocessor system operates under the newly selected master processor.

When the failed slave processor and the master processor 10 are connected to different local buses, that is, when the slave processor 20-1 fails, the following processing is performed. Master processor 1
0 sends fault information to the reset circuit 40-1 to which the slave processor 20-1 is connected. As a result, the failed slave processor 20-1 and slave processor 20-2 connected to the reset circuit 40-1 via the local buses 70-1 and 80-1.
Is electrically disconnected from the multiprocessor system.

As described above, according to the present embodiment, in the multiprocessor system in which the master processor 10 is connected to the local bus, the faulty slave processor and the master processor 10 are connected to the same local bus. Is configured to disconnect this local bus from the system. When the failed slave processor and the master processor 10 are connected to different local buses, the local bus to which the failed slave processor is connected is disconnected from the system. Therefore, it is possible to prevent the entire system from being stopped due to the failure of the slave processor in the multiprocessor system in which the master processor is not fixed.

In the second embodiment described above, the service processor is used as the new master processor selecting means, but the selecting means is not limited to this and various means can be applied. For example, Japanese Patent Application No. 8-0266
The method described in No. 79 can be applied. This is a method of selecting one slave processor from normal slave processors by a predetermined algorithm executed in a certain slave processor. As the predetermined algorithm, there is a method of assigning a number to each of a plurality of slave processors and selecting a normal slave processor having the smallest number.

[0043]

As is apparent from the above description, according to the present invention, the local bus connected to the failed slave processor is disconnected from the multiprocessor, so that the failed slave processor sends data to the local bus. Since the influence of erroneous data that may be generated can be eliminated, it is possible to prevent the entire system from being stopped.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a multiprocessor system of the present invention.

FIG. 2 is a flowchart showing the operation of the master processor 10 of the present invention.

FIG. 3 shows a slave processor 20-1, of the present invention.
And 20-4 is a flowchart showing the operation of FIG.

FIG. 4 is a block diagram showing a second embodiment of the multiprocessor system of the present invention.

[Explanation of symbols]

 10 Master processor 20-1, ... And 20-4 Slave processor 30 Main memory 40-1, 40-2 Reset circuit 50 System bus 60 System bus 70-1, 70-2 Local bus 80-1, 80- 2 Local buses 401-1 and 401-2 Failure information holding circuit

Claims (6)

[Claims] 1. A master processor, a system bus to which the master processor is connected, a plurality of slave processors, and at least one of the plurality of slave processors, respectively.
A plurality of local buses each connected to the system bus, and a plurality of local buses electrically connected between the system bus and the plurality of local buses, and connected to the plurality of local buses. If at least one of the slave processors in the fault state is included in the fault state, a connection means for disconnecting an electrical connection between the fault local bus to which the fault slave processor is connected and the system bus is provided. A multiprocessor system including :. 2. The connection means includes failure information storage means for storing failure information sent from the failed slave processor, and the failure slave is stored only while the failure information storage means stores the failure information. 2. The multiprocessor system according to claim 1, wherein the faulty local bus to which a processor is connected is electrically disconnected from the system bus. 3. A system bus, a plurality of local buses electrically connected to the system bus, a master processor connected to one of the plurality of local buses, and a local bus connected to the plurality of local buses. A plurality of slave processors, a disconnecting unit electrically disconnecting the faulty local bus connecting the faulty slave processors in the faulty state from the system bus among the plurality of local buses, and the master processor by the disconnecting unit. Is electrically disconnected from the system bus, a selecting means for newly selecting a master processor from the normal ones of the plurality of slave processors is included. 4. The local bus acquisition unit for obtaining the failed local bus to which the failed slave processor is connected, further comprising: the selecting unit connected to the failed slave processor obtained by the local bus acquisition unit. A multiprocessor system comprising: a discriminating unit for discriminating whether or not a master processor is connected to the faulty local bus, and selecting the master processor based on a discriminating result of the discriminating unit. 5. Each of the plurality of slave processors includes failure processing means for detecting a failure of its own processor and sending failure information when a failure is detected, and the disconnecting means includes the plurality of local busses. 4. The multiprocessor system according to claim 3, wherein all the processors provided for each of them are electrically disconnected when the failure information is received. 6. The plurality of slave processors have an identifier, and the selecting unit selects a new master processor from the plurality of slave processors based on the identifier. Multiprocessor system.