JP3156673B2 - Failure information transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault information transfer device used in a central office exchange and the like, and relates to a function block (hereinafter referred to as a function block) for processing an order from a host processor unit controlled by host software in accordance with a stored operation firmware. F
In the event that a failure has occurred in the function block (action block), detailed information on the failure can be immediately transferred to the host software.

[0002]

2. Description of the Related Art Conventionally, when a failure occurs in a function block, it is impossible to retrieve detailed information without having to perform initial setting again from a host software and separately read detailed data of the failure. Further, when a plurality of faults occur at once, there is a possibility that reading of fault information is delayed. Further, there is a problem that information cannot be obtained unless the failed hardware is replaced.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to promptly transfer fault information when a fault occurs in a function block, and to immediately determine a method for dealing with the fault. That is.

[0004]

According to the present invention, there is provided a fault information transfer apparatus comprising: an operating firmware storage ROM; a microprocessor operating in the operating firmware stored therein; A central office switch having a function block core unit including an order expansion circuit for expanding the order, expanding the order from the upper processor unit by the order expansion circuit, and processing according to the operation firmware stored in the operation firmware storage ROM; And the like, a failure storage firmware storing a failure firmware, a reset circuit for resetting the microprocessor of the function block core unit, a holding memory for holding failure information and the like, and a memory for transferring the failure information. An information transfer circuit and a microcomputer for controlling the information transfer circuit are provided.

When a failure occurs in the function block core unit, the microcomputer controls the reset circuit to reset the microprocessor of the function block core unit, and resets the microprocessor from the firmware storage ROM at the time of failure. In order to boot a firmware for restarting the microprocessor, the microprocessor controls so as not to boot the operation firmware from the operation firmware storage ROM, and the firmware booted from the failure firmware storage ROM is the microprocessor. Is started in the failure transfer state, and the microprocessor that starts up in the failure transfer state writes the failure information in the holding memory, and causes the failure information transfer circuit to transfer the failure information to the upper processor unit.

A highway interface circuit for transmitting the fault information held in the holding memory to the network can be further provided.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, a function block core unit (hereinafter referred to as "FB core unit") 4 of the central office exchange 4
Are connected to the upper processor unit 1 via the system bus 2. The FB core unit 4 stores the operation firmware storage ROM 8
And a microprocessor 7 operating in the firmware stored therein, an order developing circuit 9 for developing an order from the processor unit 1, and an individual circuit 6. The order from the processor unit 1 is The processing is performed in accordance with the operation firmware stored in the operation firmware storing ROM 8 and the individual circuit 6 is controlled.

The fault information transfer device 5 according to the present invention includes a fault firmware storage ROM 10 storing a fault firmware,
A reset circuit 11 for resetting the microprocessor 7 of the FB core unit 4, a holding memory 13 for holding fault information and the like, and an information transfer circuit 1 for transferring fault information
2 and a microcomputer 14 for controlling these.

When a fault occurs in the FB core unit 4, the microcomputer 14 of the fault information transfer device 5 controls the reset circuit 11, generates a reset signal, and resets the microprocessor 7. In addition, in order to boot a firmware for restarting the microprocessor 7 from the failure-time firmware storage ROM 10, the operation firmware is controlled so that the microprocessor 7 is not booted from the operation firmware storage ROM 8. Failure storage ROM 10
The firmware booted from only performs the work of writing the detailed failure information to the holding memory 13. By writing the detailed fault information to the holding memory 13, control is performed to start transferring the detailed fault information from the fault information transfer circuit 12 to the processor unit 1. The transfer is performed via the maintenance bus 3.

The above operation will be described in more detail with reference to the sequence diagram of FIG. When a failure occurs in the FB core unit 4, the microprocessor 7 of the FB core unit 4 notifies the processor unit 1 that the failure has occurred, and rewrites the failure bit to the microcomputer 14 of the failure information transfer device 5. To make a transition to the failure state. The microcomputer 14 instructs the reset circuit 11 to generate a reset signal for the microprocessor 7 by rewriting the failure bit. The microprocessor 7 is restarted by a reset signal from the reset circuit 11, but the microcomputer 14 controls the firmware booted at that time not to be taken out of the operation firmware storage ROM 8 but to the failure-time firmware storage ROM 10 instead of the operation firmware storage ROM 8. I do. When the firmware is booted from the firmware storage ROM 10 at the time of failure, the microprocessor 7 starts up in an information transfer state, not in a normal operation state. The microprocessor 7 in the information transfer state writes the detailed failure information to the holding memory 13 of the failure information transfer device 5. The microcomputer 14 controls the fault information transfer circuit 12 to transfer the fault detail information to the processor unit 1 by writing the fault detail information to the holding memory 13.

As described above, according to the present invention, the FB core unit 4 is placed in an environment where the fault information can be transferred from the fault information transfer device 5.
Can be set, even if a failure occurs in the FB core unit 4, the failure information can be transferred immediately.

FIG. 3 shows another embodiment of the present invention, which has the same basic configuration as described above, but further devises a fault information transfer device.

Referring to FIG. 3, the fault information transfer device 5a of this example not only transfers detailed fault information from the information transfer circuit 12 to the maintenance bus 3 but also includes a highway interface Can send detailed failure information over the network. By connecting to a network, it becomes possible to transfer detailed fault information to another location using a telephone line or the like. By changing the configuration of the highway interface circuit 15, it is possible to transmit data as data,
It can be converted to X information and delivered.

The present invention can be applied to a system other than the central office exchange, as long as the function block unit processes the order from the upper processor unit controlled by the upper software unit according to the operation firmware stored therein. it can.

[0016]

As described above, according to the present invention, when a failure occurs in a function block, the function block can be restarted in an environment where information can be transferred from the failure information transfer device. Even if a failure occurs in the unit, the failure information can be transferred immediately.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention applied to a central office exchange.

FIG. 2 is a sequence diagram showing an operation when a failure occurs.

FIG. 3 is a block diagram showing a configuration of another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processor part 2 System bus 3 Maintenance bus 4 Function block core part 5.5.a Failure information transfer device 6 Individual circuit part 7 Microprocessor 8 Operation firmware storing ROM 9 Order expanding part 10 Firmware storing ROM at the time of reset 11 Reset circuit 12 Information transfer circuit 13 Retention memory 14 Microcomputer 15 Highway interface circuit 16 Highway

Claims (2)

(57) [Claims] 1. An operation firmware storage ROM, a microprocessor operating in the operation firmware stored therein,
A function block core unit including an order expansion circuit that expands an order from the upper processor unit controlled by the upper software, and an order from the upper processor unit.
In a central office exchange or the like that expands in the order expansion circuit and processes according to the operation firmware stored in the operation firmware storage ROM, a failure firmware storage ROM that stores the failure firmware
A reset circuit for resetting a microprocessor of the function block core unit, a holding memory for holding fault information and the like, an information transfer circuit for transferring fault information, and a microcomputer for controlling these; When a failure occurs in the function block core unit, the microcomputer controls the reset circuit to reset the microprocessor of the function block core unit, and restarts the microprocessor from the failure-time firmware storage ROM. In order to boot the firmware for booting, the microprocessor controls so as not to boot the operation firmware from the operation firmware storage ROM, and the firmware booted from the firmware storage ROM in the event of a failure causes the microprocessor to fail. A fault information transfer characterized in that the microprocessor started up in the transfer state and started up in the fault transfer state writes fault information in the holding memory and transfers the fault information from the fault information transfer circuit to the upper processor unit. apparatus. 2. The fault information transfer device according to claim 1, further comprising a highway interface circuit for sending the fault information held in the holding memory onto a network.