JPH0713882A - Method and device for multibus control of computer system - Google Patents

Abstract

PURPOSE:To obtain a method and device for multibus control which prevents a fault from exerting influence and enables the system to continue to operate by disconnecting one system if a bus of a computer equipped with multiplied system buses becomes faulty. CONSTITUTION:In the high-reliability computer system which is equipped with the doubled system buses 10-1 and 10-2 and consists of basic processing units 11-1-11-4 connected to the system buses, input/output processing units 13-1 and 13-2, main storage devices 12-1 and 12-2, and bus controllers 1-1 and 1-2 controlling the arbitration of the multiplied system buses 10-1 and 10-2 by using a round robin system, the bus controllers 1-1 and 1-2 disconnect one system bus having the smaller number of use requests unless the multiplied system buses 10-1 and 10-2 are equal in the number of use requests.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly reliable computer system, and more particularly to a computer system multibus control method and apparatus for controlling a system bus multiplexed by a plurality of buses.

[0002]

2. Description of the Related Art In a conventional computer system, for example, as is known from Japanese Patent Laid-Open No. 62-40155, in order to improve system reliability, a system bus is composed of a plurality of buses (duplexing). ) Is done. In such a duplicated system, a fixed priority arbitration circuit is provided in the basic processing unit and the input / output processor, and if there is a discrepancy between the usage requests of the duplicated system buses, the use of the system bus is permitted. It is known to monitor the responses of the basic processing unit and the input / output processor to determine the faulty system and disconnect it.

Further, for example, according to Japanese Patent Laid-Open No. 3-233744, in such a multiplexed high reliability computer system, when an error occurs in the operating system, one channel bus is duplicated to another channel bus. , A processing system having a dual central controller and a channel controller for switching to a spare system including a spare channel bus is disclosed.

Further, according to JP-A-3-271849, one control unit and a plurality of controlled units are composed of a request bus and a response bus, which are different from the above-mentioned multiplexed system bus. There is known a system in which a system bus called a multibus is used to perform centralized monitoring by a monitoring circuit of a multibus connection control unit. That is, a fault of one controlled unit is caused by a connection failure caused by inserting / removing a package forming the controlled unit into / from a back panel forming the multi-bus, and causing a failure of one controlled unit to another controlled unit connected to the same bus. In order to prevent a so-called bus lock failure from spreading, it is known that a check circuit determines whether or not the response signal of the controlled unit is normal.

[0005]

In the above-mentioned prior art, the priority of use of the multiplexed system buses is fixed, and at the same time, the arbitration circuit is distributed in each input / output processor. , It was possible to judge the faulty system. However, when the arbitration circuits are centrally arranged at one place and the priority order is determined by using the round robin, there is a problem that the failure system cannot be determined by the conventional technique.

Further, according to Japanese Patent Application Laid-Open No. 3-233744, switching to a standby route is performed when an error occurs in the operating system in a processing system including a duplicated central controller and channel controller. In order to carry out without trouble, test the standby route by checking the signal level Although the test method is described,
It does not teach any method of detecting an abnormality of a device connected to the system bus and prioritizing use of the system bus.

Further, a system in which a system bus called a multibus composed of a request bus and a response bus, which is known from Japanese Patent Laid-Open No. 3-271849, is centrally monitored by a multibus connection control unit monitoring circuit is a system A device connected to the system bus has a different technical meaning from the multiplex of the system bus for high reliability, and its controlled unit is selected by a selector, but its disconnection condition is also different. It does not teach how to detect abnormalities and prioritize use of the system bus.

Therefore, in view of the above-mentioned conventional technique, an object of the present invention is to enable the system operation to be continued when determining the priority order of the system buses multiplexed by using round robin. It is possible to determine which of the two systems is to be disconnected, and further to provide a multi-bus control method for a computer system and a device therefor capable of detecting a failure part. Here, the round robin is a method of determining the priority order in which the second priority order has the highest priority next time.

[0009]

To achieve the above object, according to the present invention, there is provided a multiplexed system bus, a basic processing unit connected to the multiplexed system bus, and the multiplexed system bus. I / O processing unit connected to a multiplexed system bus, a storage device connected to the multiplexed system bus, and bus control for controlling arbitration of the multiplexed system bus using a round robin method In a computer system including a device, a multi-bus control method for a computer system has been proposed in which the bus control device disconnects the system bus based on the number of usage requests of each bus of the multiplexed system bus.

Another object of the present invention is to provide a basic processing unit having a multiplexed system bus, connected to the multiplexed system bus, and an input connected to the multiplexed system bus. A computer system comprising an output processing unit, a storage device connected to the multiplexed system bus, and a bus controller for controlling arbitration of the multiplexed system bus using a round robin method, wherein the bus The control unit is achieved by a multi-bus control unit of a computer system, which comprises means for disconnecting the system bus based on the number of usage requests of each bus of the multiplexed system bus.

[0011]

That is, according to the above-described method and apparatus for controlling a multi-bus of a computer system according to the present invention, the use of each of the above-mentioned buses, such as when there is a mismatch in the number of requests for use of the buses in a multiplexed system bus. By the function of disconnecting the system bus based on the number of requests, only part of the system bus is disconnected, but in that case, only the bus that has no or few requests is disconnected, so the system operation can be continued. In addition, the bus can be reliably disconnected without affecting the failure.

[0012]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. First, FIG. 2 shows an overall schematic diagram of a high reliability computer system (FTC) to which the multibus control method for a computer system and its apparatus of the present invention are applied.
In this system, there are two sets of system buses 1 for duplication.
0-1, 10-2 are provided, and one or a plurality of basic processing units (BPU) 11-1, 11-2, 11-3, 11-4 are provided on these buses.
And a bus controller (BC) 1-1 for controlling one system bus (SB) 10-1, a bus controller (BC) 1-2 for controlling the other system bus (SB) 10-2, Furthermore, input / output processors (IOU) 13-1, 13 connected to files and networks
-2 is connected to the system buses 10-1 and 10-2, respectively. A main storage unit (MSU) 12-1 is connected to the system bus 10-1, and the system bus 10-
Another main storage unit (MSU) 12-2 is connected to 2. In this embodiment, the bus controller (B
C) 1-1, 1-2, main memory unit (MSU) 12-1,
12-2 and input / output processor (IOU) 13-
Two of each of the units 1 and 13-2 are used as one set, and each of these sets is used. In this figure, for ease of understanding, each of the redundantly provided constituent elements corresponding to the duplicated system buses 10-1 and 10-2 has an A or B is displayed (A system, B system).

FIG. 1 shows a bus controller (BC) 1-
The internal structure of 1, 1-2 is shown. In the figure, bus controllers (BC) 1-1, 1-2 are bus use requests 2-1, 2-2, 2-3, 2- that are signals from the outside.
4 to 2 signals, that is, bus use permission 3-1 and 3-
Dualized arbitration circuits 6-1, 6-2, 6 for making 2
-3, 6-4 and a comparator 7-which compares the output results of the arbitration circuits in order to check the outputs.
1, 7-2, and further the bus use requests 2-1, 2
-2, 2-3, size comparator 5 for comparing the magnitude of 2-4
1 and 5-2, and from the comparison results of these magnitude comparators, two signals, bus disconnection 4-1, 4
-2 is output.

According to the present invention, the bus use request 2-
When there is a discrepancy between 1, 2-2, 2-3, and 2-4, the size comparators 5-1 and 5-2 determine the magnitude of the number of bus usage requests, and the system having the few number of bus usage requests. Signal for disconnecting the bus of, the bus disconnection signal 4-1 (that is,
System bus 10-1 (system A) disconnection or bus disconnection signal 4-2 (that is, system bus 10-2)
By outputting (separation of (B system)), it is possible to prevent one failure of the system bus from spreading within the system.

Next, FIG. 3 shows a time chart of the signals of the respective parts during normal operation. First, from the top of the figure, the basic processing unit (BPU) 11
The waveform of the A system bus use request 2-1 of -1 is the A of the basic processing unit (BPU) 11-2.
The waveform of the system bus use request 2-2 is shown. Below that, the waveform of the B-system bus use request 2-3 of the basic processing unit (BPU) 11-1 is further displayed.
The waveforms of the B-system bus use request 2-4 of -2 are shown. That is, when there is a bus use request from both the basic processing unit (BPU) 11-1 and the basic processing unit (BPU) 11-2, and here, the basic processing unit is more important than the basic processing unit (BPU) 11-1. Assuming that (BPU) 11-2 has a higher priority, bus usage permission 3 is first given to the basic processing unit (BPU) 11-2 as shown in the signal waveform of bus usage permission 3 in the figure. (Indicated by "2" in the signal waveform in the figure). As a result, the basic processing unit (BPU) 11-2 outputs the bus use signal 20 having a waveform at the bottom of the figure. After that, the bus use permission 3 is given to the basic processing unit (BPU) 11-1 by round robin (indicated by "1" in the waveform of the bus use permission 3 in the figure), and the basic processing unit (BPU) 11-1 The bus use signal will be output.

4 to 6, the bus use request 2 is shown.
An example in the case where a mismatch occurs between -1, 2-2, 2-3, and 2-4 and a time chart of the signal waveform of each part at that time are shown. First, FIG. 4 shows a case where there is no bus use request 2-4 which is a signal (indicated by a broken line), that is, a case where only the bus use request 2-4 has no bus use request. In such a case, it is not possible to determine which system has failed. However, if either system is not disconnected, the bus use permission is issued to different devices in both systems, which causes different devices to simultaneously use the system bus.

Therefore, in the present invention, in such a case, the system with less demand for bus use, the B system in the example shown in FIG. 4, is disconnected.
That is, as shown in FIG. 5, the bus usage request 2 of the A system of the basic processing unit (BPU) 11-2
When 2 is mistakenly turned on, that is, when there is a so-called on failure, a bus use permission 3 which is a permission signal is returned to the faulty device, but since the bus use signal 20 is not returned from that device, By the round robin, the bus use permission 3 is given to the next device immediately, and in the case of such an ON (ON) failure, the processing can be continued without disconnecting the failed A system.

On the other hand, as shown in FIG. 6, the bus processing request 2-4 of the B system of the basic processing unit (BPU) 11-2 is in the off state (OFF) although it is in the on state. In the case of a so-called OFF failure, a bus use permission 3 which is a signal for permitting use of the bus is output to the B system, and unless the B system is disconnected, the bus use permission is given to different devices in both systems. Will occur, and different devices will simultaneously use the system bus, which will spread the failure in the system. In this case, by disconnecting the system having the smaller number of requests for bus use, the operation of the device actually making the request for bus use is enabled. At the same time, the bus disconnection 4-2, which is a signal for disconnecting the system with a small number of requests for bus use, in the above case, the B system is turned on (set to “HIGH”).
As a result, the spread of the failure can be prevented.

The above-described operation will be described with reference to the flowchart of FIG. 7. In step st1, the bus controller (BC) accepts the bus use request, and in the next step st2, the accepted bus use request becomes one. Judge whether or not you are doing. As a result, if it is determined that they match (Y), the process proceeds to step 6, where the normal operation, which is the operation operation at the normal time, is performed. On the other hand, if it is determined that they do not match (N), the process proceeds to the next step st3, and it is determined which of the A system and the B system has a smaller number of bus use requests. As a result, if it is judged that the number of A-systems is small (A), the bus of the A-system is disconnected as shown in step st4, while if the bus-use request of the B-system is small, it is as shown in step st5. Then, the B system bus is disconnected.

By the way, in the embodiment described above, A
It is impossible to determine which system, system B or system B, has failed, and which device has failed. In view of this, in the present invention, a second embodiment is shown in FIG. 8 and FIG. 9, which makes it possible to determine which device in which system has a failure.

Similar to FIG. 4, FIG. 8 shows the internal structure of the two bus controllers (BC) 1-1 and 1-2, and in this figure, the respective size comparators 5- are shown.
1, 5-2 together with the respective faulty device storage registers 2
1-1 and 21-2 are provided. The failure device storage registers 21-1 and 21-2 are provided in the size comparator 5 described above.
-1, 5-2 receives signals 22-1, 22-2 indicating the device numbers for which the bus use requests 2-1, 2-3 or the bus use requests 2-2, 2-4 do not match, and Bus use signals 20-1, 20-2 for use permission 3
A flag is set when (see FIGS. 5 and 6) is not returned. These failure device storage registers 21-1,
By providing 21-2, as shown in Table 1, it is possible to determine which device in which system has a failure.

[Table 1]

For example, when the A system is disconnected, it is determined that the A system is in failure when the device whose bus usage request 2 does not match is using the bus, and the B system is in failure when the bus is not used. You can When the B system is disconnected,
When the device that did not match the bus usage request 2 used the bus, the B system was faulty, and when the device did not use the bus,
It can be judged that the A system is out of order. These can be summarized as shown in Table 1 above, and it is clear that it is possible to determine which device in which system is in failure by these failed device storage registers 21-1 and 21-2. Is.

The details of the above operation will be described with reference to the flowchart of FIG. This flowchart is for determining a faulty device in addition to the flowchart shown in FIG. 7, and steps st1 to st6 are the same as those in FIG. 7, and description thereof will be omitted here.
Then, in this flowchart, the bus disconnection (s
After performing t4, st5), steps st7 and st
At 8, it is judged whether or not the bus use signal 20 (see FIGS. 5 and 6) is returned from the device whose bus use requests do not match, and the failure system is judged. Specifically, A
If a bus use signal is returned from a device whose bus use request does not match when the system is disconnected, it is determined that the A system is in failure (step st9), and if the bus use signal is not returned, the B system is in failure. It is determined (step st10). Also,
If a bus use signal is returned from a device whose bus use request does not match when the B system is disconnected, it is determined that the B system is in failure (step st10), and if the bus use signal is not returned, A
It is determined that the system is out of order (step st9).

[0024]

As is clear from the above detailed description, according to the multi-bus control method and apparatus for a computer system of the present invention, even in a centrally arranged round robin arbitration circuit, a system bus use request is made. In the event of a discrepancy between the two, it is possible to reliably disconnect one system, prevent the spread of failures, and continue the processing of the system, and it is also possible to detect the failed part. Exert the effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a detailed structure of an apparatus for implementing a multi-bus control method for a computer system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the overall configuration of a computer system that is an embodiment of the present invention.

FIG. 3 is an output waveform diagram of each unit for explaining the operation of the multi-bus control device when the system bus is normal.

FIG. 4 is an explanatory diagram for explaining the operation of the multi-bus control device when the system bus fails.

FIG. 5 is an output waveform diagram of each part for explaining the operation of the multi-bus control device when the system bus has an ON failure.

FIG. 6 is an output waveform diagram of each unit for explaining the operation of the multi-bus control device when the system bus is off.

FIG. 7 is a flowchart for explaining the operation of the multibus control device.

FIG. 8 is a block diagram showing a configuration of a multi-bus control device according to another embodiment of the present invention.

FIG. 9 is a flowchart illustrating an operation of the multibus control device according to another embodiment.

[Explanation of symbols]

 1 bus controller 2 bus use request signal 3 bus use permission signal 4 bus disconnection signal 5 magnitude comparator 6 arbitration circuit 7 comparator 10 system bus 11 basic processing unit 12 main memory device 13 input / output processor 20 bus usage signal 21 fault device memory Register 22 Signal that indicates bus usage request disagreement device

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Hiroaki Fukumaru Inventor Hiroaki Fukumaru 2-5-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Co., Ltd. Omika factory (72) Inventor Yoshihiro Miyazaki 5-chome, Omika-cho, Hitachi-shi, Ibaraki No. 1 in stock company Hitachi Ltd. Omika factory

Claims (15)

[Claims] 1. A basic processing unit comprising a multiplexed system bus, connected to the multiplexed system bus, an input / output processing unit connected to the multiplexed system bus, and the multiplexing. In a computer system comprising a storage device connected to a system bus and a bus controller that controls arbitration of the multiplexed system bus using a round robin method, the bus controller is the multiplexed device. A multi-bus control method for a computer system, characterized in that the system buses are disconnected based on the number of usage requests of each system bus. 2. The multi-bus control method for a computer system according to claim 1, wherein the bus control device compares the number of use requests of each bus of the multiplexed system bus, and the number of use requests is small. A multi-bus control method for a computer system, characterized in that the system bus is disconnected. 3. The multi-bus control method for a computer system according to claim 1, wherein the bus control device detects a mismatch in the number of usage requests of each bus of the multiplexed system buses, and the mismatch is detected. A multi-bus control method for a computer system, characterized in that the system bus is disconnected based on the number of usage requests of each bus of the multiplexed system bus. 4. The multi-bus control method for a computer system according to claim 3, wherein after disconnecting the system bus, it is detected whether or not there is a bus use signal from a device in which a mismatch in the number of use requests of the bus is detected. A multi-bus control method for a computer system, comprising: determining a fault system of the multiplexed system buses based on the detection result. 5. A basic processing unit comprising a multiplexed system bus, connected to the multiplexed system bus, an input / output processing unit connected to the multiplexed system bus, and the multiplexing. In a computer system comprising a storage device connected to a system bus and a bus controller that controls arbitration of the multiplexed system bus using a round robin method, the bus controller is the multiplexed device. A multi-bus controller for a computer system, comprising means for disconnecting the system bus based on the number of requests for use of each system bus. 6. The multi-bus controller of the computer system according to claim 5, wherein the bus controller compares the number of usage requests of each bus for each of the multiplexed system buses. A multi-bus controller for a computer system, characterized in that it comprises a comparison means. 7. The multi-bus controller of the computer system according to claim 5, wherein the bus controller includes comparators for detecting a mismatch in usage request numbers of the buses of the multiplexed system buses, respectively. A multi-bus control device for a computer system, which is provided. 8. The multi-bus controller of the computer system according to claim 5, wherein the bus controller is provided for each bus of the multiplexed system buses, and each bus controller has its own system bus. A multibus controller for a computer system, comprising a plurality of arbitration means for arbitrating in response to a bus use request from the computer. 9. The multibus controller for a computer system according to claim 5, wherein the bus controller further comprises storage means for storing a failure device. Control device. 10. The multi-bus controller of the computer system according to claim 8, wherein the outputs from the plurality of arbitration means are compared to detect a mismatch in the number of usage requests of each bus of the multiplexed system buses. A multi-bus controller for a computer system, which is provided with a comparator for performing the operation. 11. The multi-bus controller of the computer system according to claim 8, wherein each of the bus controllers compares the number of usage requests of each bus for each of the multiplexed system buses. A multi-bus controller for a computer system, comprising: a magnitude comparison device for outputting a signal for disconnecting a system bus with a small number of requests for use. 12. The multi-bus controller of the computer system according to claim 8, wherein each of the bus controllers is a failure device for storing a failure device for each bus of the multiplexed system bus. A multi-bus controller for a computer system, comprising a storage register. 13. The multibus controller for a computer system according to claim 12, wherein the failed device storage register stores the number of a device whose bus usage request does not match. Control device. 14. The multibus controller of the computer system according to claim 13, wherein the faulty device storage register further sets a flag when a bus use signal is not returned in response to a bus use permission. Computer system multi-bus controller. 15. The computer system according to claim 5, wherein the multibus controller of the computer system is used for controlling disconnection of a system bus of a high reliability computer having a multiplexed system bus. Multi-bus controller.