JPH05346864A - Fault processing system for information processor - Google Patents

Abstract

PURPOSE:To exactly grasp a power supply fault and to deal with this fault by changing the bit information of a maintenance registration part at a host device based on fault information received through a common bus and detecting the presence/absence of the power supply fault at the host device from the changed bit state while referring to this maintenance registration part. CONSTITUTION:This system is provided with a shelf 15 to store input/output controllers 14 to input/output devices 13 every group of devices, power supply package 16 to supply power to each shelf 15, and maintenance registration part 17 provided in a host device 11 and displaying a power supply state based on power supply information from the power supply package 16. When any abnormality is generated at the power supply package 16, the abnormality is reported through a common bus 12 to the maintenance registration part 17 and while referring to this maintenance registration part 17, the host device 11 detects the power supply fault. This power supply information shows the presence/absence of a power supply output of each power supply package 16 and/or the normality/abnormality of the power supply output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a telephone exchange system and, more particularly, to a technique effective when applied to fault handling when a power source fails.

[0002]

2. Description of the Related Art A control system of an information processing apparatus of this type, for example, an electronic exchange, is composed of a plurality of processing devices.
The respective device configurations are generally such that a plurality of input / output devices are connected in a branch manner to a host device such as a processor or a channel device via a common bus. A device configuration of this type is shown in FIG.

The device configuration shown in FIG.
F) and a standby system (MATE), each of which has a central processing unit (CC), a main memory unit (MM), a channel control unit (CHC), and an input / output control unit (IOC).

The central processing unit (CC) uses the duplex system to set the first central processing unit (CC-0) to the active system (SELF) and the second central processing unit (CC-1) to the standby system (MATE). (The two are collectively referred to as a central processing unit (CC) unless otherwise specified). The central processing unit (CC) is for performing main control of the device, resource (trunk, network, etc.) management, fault handling, and maintenance operation processing. The main memory (MM) is directly accessed by the central processing unit (CC),
It is composed of a basic storage unit and an extended storage unit. The channel controller (CHC) controls the input / output device (IOD) independently of the central processing unit (CC), and the common bus (C-
A plurality of input / output control devices (IOCs) are connected in a branch shape via a bus.

The input / output control device (IOC) is housed in a housing called a shelf (SH) for each fixed number of input / output device groups, and a package power supply (POW) is provided for each shelf (SH). Has become.

In the figure, INF is an interface and functions to connect common buses (C-BUS) for each shelf (SH).

[0007]

In the device configuration described above, when the power supply in the shelf (SH) is cut off, the input / output control device (IO) in the shelf (SH) is shut off.
Since all of C) do not function, I / O devices (I
OD) was all unusable.

However, in the case where the power failure occurs, in the prior art, in the host device such as the central processing unit (CC) or the channel control unit (CHC), the input / output control unit (IOC) or the input / output unit ( It could be detected only as a functional failure of (IOD), and it was difficult to identify the cause of the failure.

From this point of view, a configuration may be considered in which metallic wiring is directly provided from the power source system to detect the operating / non-operating state of the power source package (POW). For example, such a non-operating state is brought about. At the time, it was unclear whether the power was artificially cut off for maintenance or due to a power failure.

The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of accurately grasping a power supply failure and coping with the power supply failure in an information processing apparatus.

[0011]

The present invention has the following configuration as a failure processing method of an information processing apparatus for solving the above problems, and will be described with reference to FIG.

In the information processing apparatus in which a plurality of input / output devices 13 are connected to the host device 11 via the common bus 12, the shelf 15 includes an input / output control device 14 for the input / output devices 13 for each group of devices. It is to be housed. The power supply package 16 supplies power to each of the shelves 15.

The maintenance registration unit 17 is used by the host device 11
The power supply state is displayed on the basis of the power supply information provided from the power supply package 16.

[0014]

In the first aspect of the invention, first, when the power supply to one of the shelves 15 is cut off or the power supply is abnormal, this information is sent to the host device 11 through the common bus 12. In the higher-level device 11, for example, the bit information of the maintenance registration unit 17 changes based on the failure information received via the common bus 12. The higher-level device 11 refers to the maintenance registration unit 17 to detect the presence / absence of power failure from the changed bit state.

In the second aspect of the invention, each bit of the maintenance registering section 17 such as presence / absence of power supply output, normality / abnormality of power supply, etc. when the fault condition is sent to the host device 11 through the common bus 12 according to the first invention. More detailed fault content can be specified by the composite condition of the states.

Further, in the third invention, the host device 11 is
First, the input / output control device 14 or the input / output device 13 is accessed. When there is an abnormality in this access, this is recognized as a hypothetical functional failure for the time being, and then the presence or absence of the power failure described in the first invention is detected. If it is a failure of the power supply package 16, the processing is performed as a power supply failure, and if it is detected that the power supply is normal, the processing is performed as a functional failure of the input / output control device 14 or the input / output device 13. To do.

Further, according to the fourth aspect of the invention, the passage selecting means 21 is provided in the shelf 15, and when the power source fails, the common bus 12 is connected to the bypass passage 20 to bypass the faulty shelf 15. Data can be sent to other normal shelves. As the passage selecting means 21, for example, a relay that operates electromagnetically or electronically can be used.

[0018]

EXAMPLES Next, examples of the present invention will be described.

FIG. 2 shows a fault information notification route centered on the central processing unit (CC). Although the channel controller (CHC) is omitted in the figure, the common bus (CB)
Power failure information from each shelf (SH) is notified by a power failure notification signal (PAL) and a power output notification signal (NOP) in US). The input / output paths of the central processing unit (CC) are the active system (S
ELF) and a backup system (MATE),
The central processing unit (CC) has a shelf (S) connected to the other central processing unit (CC) not shown in FIG.
The power supply abnormality notification signal (PAL) and the power supply output notification signal (NOP) from H) are also available. FIG. 3 shows the notification paths of the power supply abnormality notification signal (PAL) and the power supply output notification signal (NOP) between the shelves (SH). As is clear from the figure, each shelf (S
A power supply abnormality notification signal (PAL) is output from the package power supply (POW) in H). This power supply abnormality notification signal (PAL) is output to the common bus (C-BUS) through the interface (INF) in the shelf (SH) to which the power supply abnormality belongs.
The interface (INF) in the shelf (SH) is provided with a relay 1 as a path selecting means, and the operating state of the relay 1 is output to the common bus (C-BUS) as a power output notification signal (NOP). It is supposed to be done. The relay 1 may be either an electromagnetic contact relay 1 or an electronic non-contact relay 1.

FIG. 4 shows a common bus (C-BU) other than the above.
The connection route of the signal line on S) is shown.

The common bus (C-BUS) from the channel controller (CHC) has a bus power supply line 2 of, for example, 5V.
, A general data line 3 for transmitting / receiving data, and a pair of control lines (RQ) for transmitting / receiving a data request signal and a data reception signal.
DT, ACDT) and input / output data control lines (ACDT1, ACI0-3) from the channel controller (CHC) to each input / output controller (IOC).

The power supply line 2 for the bus and the general data line 3
And the control line (RQDT, ACDT) are connected to the bus (SH-BUS) in the shell from one interface (INF).
To another shelf (SH) via another interface (INF).

A relay 1 as a path selecting means provided in the interface (INF) connects the input / output data control lines (ACDT1, ACI0-3) to a bypass signal path (B-PASS) and a normal signal path (N-). PASS). The relay 1 selects the normal signal path (N-PASS) side in a normal state, that is, when the power source is normal.

An input / output controller (I) in the shelf (SH)
OC), the normal signal line (N-
Data is exchanged with the input / output device (IOD) via PASS).

In the device configuration shown in FIG. 4, the power supply in the shelf (SH) is cut off and each input / output control device (IO) is disconnected.
If C) fails, the relay 1 operates and the bypass signal path (B-PASS) is selected immediately. As a result, all the input / output control devices (IOC) in the same shelf (SH) are disabled, but the input / output control devices (IOC) of other shelves (SH) not shown are relieved.

FIG. 5 shows the bit configuration of the maintenance registration unit (MFFG) provided in the central processing unit (CC). The maintenance registration unit (MFFG) is composed of, for example, a flip-flop group element that constitutes a 32-bit register, and is capable of comprehensively detecting power failure information depending on the state of each bit.
Further, FIG. 6 shows the meaning of each bit.

The fault condition will be described below with reference to FIGS. 5 and 6. Bits 00 to 17 indicate the power supply state of the central processing unit (CC) of the active system (SELF). Of these, 00 bits and 01 bits are the central processing unit (CC).
It is cleared by hardware when is turned on or reset. 24 to 31 bits are each channel control device (CH
C) (in the present embodiment, the channel control device (CHC0 to CHC0
3)) power supply output notification bit and power supply abnormality notification bit.

For example, the 24th bit indicates the presence / absence of power supply output in the input / output control unit (IOC) under the control of the channel control unit (CHC) 0, which is set by the above-mentioned power supply output notification signal (NOP). Bit is "
When it is 1 ", it indicates that it is in the non-operation state. Further, corresponding to the 24th bit, the 28th bit is in the input / output control unit (IOC) under the control of the channel control unit (CHC) 0. It indicates the presence or absence of power failure, and it is set by the power failure notification signal (PAL). When the bit is "0", it indicates normal or non-operation status. When it is "1", power failure is indicated. Shows.

Next, the processing flow when a failure occurs will be described with reference to FIG. First, when the power is cut off or a power failure occurs in any of the shelves (SH) (701), the relay 1 operates and the bypass signal path (B-PASS) is selected (702), and each input / output control device ( The failed shelf (SH) is bypassed for the I / O control signal to the IOC.

Next, the information about the power output and the power failure is sent to the central processing unit (C) via the common bus (C-BUS).
Notify C). In the central processing unit (CC), this changes the predetermined bit state of the maintenance registration unit (MFFG) (703).

On the side of the central processing unit (CC), regarding the failure in the shelf (SH), the input / output control unit (I
OC) or the input / output device (IOD) itself is detected as a hypothetical malfunction (704).

Next, the central processing unit (CC) reads the maintenance registration section (MFFG) and checks the power supply state (705). At this time, the power output notification bit is "0"
When in the (operation) state and the power supply abnormality notification bit is "0" (no abnormality), it is not the power supply failure but the actual input / output control device (IOC) or input / output device (IOD) function failure. Because (70
6) Then, the routine proceeds to the function failure processing routine (707).

If the power supply output notification bit is "1" (non-operation) or the power supply abnormality notification bit is "1" (abnormal) in step 706, each status of the maintenance registration unit (MFFG) is used as a message and C
Output to RT display or printer (70
8).

Next, the central processing unit (CC) sequentially accesses each input / output control unit (IOC) in the shelf (SH) to relieve the operable input / output control unit (IOC) and at the same time operate. The input / output control unit (IOC) in the defective state is disconnected (709). Finally, the information of the input / output control device (IOC) and the input / output device (IOD) having the failure is output (710).

As described above, according to this embodiment, the central processing unit (CC) refers to the maintenance registration unit (MFFG), so that the fault condition can be accurately grasped by the composite condition of each bit. That is, the power supply package (POW) of a specific shelf (SH) due to maintenance, etc.
When the power is shut off, the maintenance registration unit (MFFG) corresponding to the shelf (SH) has the power output notification bit set to “1” and the power failure notification bit set to “0”. It is possible to instantly detect that the power is artificially cut off.

[0036]

According to the present invention, it is possible to detect a power failure in an information processing apparatus quickly and accurately.

With this, when a functional failure or a power failure occurs in the information processing apparatus, the failure can be quickly recovered.

[Brief description of drawings]

FIG. 1 is a principle diagram showing the principle of the present invention.

FIG. 2 is a block diagram showing a fault information notification path from each shelf to the central processing unit in the embodiment of the present invention.

FIG. 3 is a block diagram showing a fault information notification path between each shelf in the embodiment of the present invention.

FIG. 4 is a block diagram showing signal paths on a common bus in a shelf in the embodiment of the present invention.

FIG. 5 is a block diagram showing a bit configuration of a maintenance registration unit in the embodiment of the present invention.

FIG. 6 is an explanatory diagram showing the states of bits and the meanings of failures in the embodiment of the present invention.

FIG. 7 is a flowchart showing a processing procedure when a failure occurs in the embodiment of the present invention.

FIG. 8 is a block diagram showing a device configuration of an information processing device.

[Explanation of symbols]

 1 relay 2 bus power supply line 3 general data line 11 host device 12 common bus 13 input / output device 14 input / output control device 15 shelf 16 power supply package 17 maintenance registration unit C-BUS common bus CC central processing unit CHC channel control unit IOC input Output controller POW Package power supply SH Shelf.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Yoshioka 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Hisamitsu Tanihira, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Takeshi Yamamoto 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Nakano, 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture Fujitsu Communication Systems Ltd.

Claims (4)

[Claims] 1. An information processing apparatus in which a plurality of input / output devices (13) are connected to a host device (11) via a common bus (12), and an input / output control device for the input / output device (13). A shelf (15) accommodating (14) for each group of devices, and a power supply package (1 for supplying power to each shelf (15)
6) and a maintenance registration unit (17) that is provided in the host device (11) and displays the power status based on the power information from the power package (16). When it occurs, an abnormality is notified to the maintenance registration unit (17) via the common bus (12), and the host device (11) refers to the maintenance registration unit (17) to detect a power failure. A failure processing method for an information processing device, which is characterized by detecting. 2. The power supply failure processing of the information processing apparatus, wherein the power supply information according to claim 1 is information indicating presence / absence of power supply output and / or normality / abnormality of power supply output for each power supply package (16). method. 3. The host device (11) according to claim 1, when the host device (11) accesses the input / output control device (14) or the input / output device (13) and there is an abnormality, this is first hypothesized. Detected as a functional failure, then common bus (12)
If the occurrence of a power failure is detected based on the power information from the device, it is treated as a power failure, and only when it is not a power failure, the functional failure of the input / output control device (14) or the input / output device (13) itself. A failure processing method for an information processing device that processes as. 4. An information processing device in which a plurality of input / output devices (13) are connected to a host device (11) via a common bus (12), and an input / output control device for the input / output device (13). A shelf (15) accommodating (14) for each group of devices, and a power supply package (1 for supplying power to each shelf (15)
6) and the normal passage (18) from the common bus (12) to each input / output control device (14) in the shelf (15) is bypassed and directly connected to another shelf (15). And a passage selecting means (21) for switching to the bypass passage (20), when a power failure occurs in the shelf (15),
The passage selecting means (21) is activated to operate the common bus (12).
Is connected to another normal shelf (15) by bypassing the shelf (15) in which the power failure has occurred.