JP2000322102A - Duplexed constitution for process input/output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the occupation ratio of an I/O bus and the load of a processor in a transmission control module. SOLUTION: Each I/O device is provided with a switch SW for transmitting an operation/stand-by switching command to each of processors of duplexed I/O modules 91A, 91B to 98A, 98B through a signal line CH, so that the operation/stand-by switching of each of the I/O modules can be executed in each process I/O device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a dual configuration of a process input / output device which directly interfaces with a controller of a distributed control system via an IO link.

[0002]

2. Description of the Related Art A conventional distributed control system is configured, for example, as shown in FIG. In the figure, 1 is a man-machine interface device, 2 is a control LAN (local area network), and 31 to 3n are controllers. That is, a plurality of controllers (several tens in the case of a large-scale) distributed and installed are connected to the control LAN 2.
And manages them with one to several man-machine interface devices 1.

FIG. 4 shows a controller (31) in FIG.
An example of the configuration will be described. In the figure, reference numeral 4 denotes a control MPU (microprocessor unit), 5 denotes an IO link, and 61 to 6n denote process input / output devices. That is, the control MPU 4 performs an operation for process control, and a plurality of (for example, 32) process input / output devices 61 to 6n distributed and installed.
And data exchange via the IO link 5. The process input / output devices 61 to 6n are connected to various sensors and actuators of the process, and control the analog amount of the process.
It is converted into a digital quantity that can be calculated by U4.

In such a system, controllers 31 to 3n may be duplicated as shown in FIG. 5 in order to improve reliability. In FIG. 5, 4A and 4B are control MPUs, 5A and 5B are IO links, and 61 to 6n are process input / output devices. Here, the control MPUs 4A, 4B and the IO links 5A, 5B are duplicated, and the IO links 5A, 5B,
Process input / output devices 61 to 6n are connected to 5B, respectively.

FIG. 6 shows a process input / output device 6 corresponding to the duplexing of the control MPUs 4A and 4B and the IO links 5A and 5B.
1 to 6n show configuration examples. In the figure, 5A and 5B are IO links, 7A and 7B are transmission control modules, and 8 is I link.
O buses 91 to 9n are IO modules. here,
Transmission control modules 7A and 7B are IO links 5A and 5B
Interface with the I / O bus 8 and the control MPU 4
A, 4B relays data exchange between the IO modules 91 to 9n. On the other hand, the IO modules 91 to 9n directly interface with the process and perform conversion between analog quantities and digital quantities. In the example of FIG.
The transmission control modules 7A and 7B are duplicated corresponding to the duplication of the U4A and 4B and the IO links 5A and 5B. 7A, 7B
Is switched.

[0006] The above-mentioned ones have the following disadvantages. (1) Although the transmission control module in FIG. 6 is duplicated, the IO module is not duplicated. For this reason, if an abnormality occurs in any of the IO modules, monitoring and control of the processes connected to the IO module become impossible, which may be a significant drawback in some systems. (2) Similarly, the IO bus is not duplicated. Therefore, when an abnormality occurs in the IO bus, all the IO modules connected to the IO bus become unusable, which may also be a serious drawback in some systems.

[0007] Therefore, the applicant filed Japanese Patent Application Laid-Open No. 10-22220.
No. 4 has proposed a system as shown in
It is simply called the proposal method). FIG. 7 is a configuration diagram showing the proposed method. In the figure, reference numeral 61 denotes an IO shelf, which has mounting slots for mounting two transmission control modules 7A, 7B and 16 IO modules 91A, 91B to 98A, 98B, and one IO shelf. Constitute one process input / output device.

Also, 5A and 5B are IO links, 8A and 8
B is an IO bus, and IO modules 91A and 91B to
98A and 98B have slot numbers 00, 01 and 02, respectively.
,..., And 14 are assigned, and the same type of IO modules 91, 92,... One pair of the IO modules A and B operates on one side and the other on standby, and both are connected to the process. The input signal from the process is input to both the operation and the standby, and the signal output to the process is performed only by the operation side.

Further, the transmission control module 7 of the duplex pair
Between A and 7B and between IO modules 91A and 91B to 98
A and 98B are connected to a duplex setting and an operation / standby switching signal D, respectively. FIG. 8 shows an example of a process input / output device having an operation / standby switching circuit operated by the switching signal D, and FIG. 9 shows a time chart thereof. Although FIG. 8 shows the IO modules 91A and 91B, the transmission control modules 7A and 7B are configured in substantially the same manner.

[0010] The * MSTC signal in FIG. 8 is a signal representing the microprocessor 102A of each IO module 91A, 91B,
102B is an operation / standby control signal controlled by * W
The DTE signal is output from the watchdog timer monitoring circuit 12 implemented by hardware of each of the IO modules 91A and 91B.
9A and 129B overflow signals.
Input to R gates 110A and 110B. * RST signal is a reset signal generated by reset pulse generation circuits 111A and 111B of each of IO modules 91A and 91B when power is turned on, and is a JK flip-flop (JK ·
FF) 112A, 112B, 113A, 113B.

SLT0 and SLT1 are signals indicating the number of the slot in which the IO modules 91A and 91B are mounted, and the IO module connection connectors 120A and 12A installed on the motherboard of the IO shelf 61.
A predetermined pin of 0B is short-circuited to 0V or pulled up to + 5V and set for each mounting position. In the figure, the number of signal lines for recognizing slot numbers is two, but when the number of slots of the IO shelf 61 is 16, four signal lines are used.
Two signal lines are required. FIG. 8 shows a simple example in which the number of slots is four and the number of signal lines is two.

Next, the operation of this circuit will be described with reference to the time chart of FIG. Now, IO module 91
When power is supplied to A and 91B and the reset signal * RST is released, the microprocessors 102A and 102B of the IO modules 91A and 91B recognize the slot numbers. In the case of the IO module 91A, the slot number is an even number (in the illustrated example, SLT0 = "0", SLT1 =
“0”), the * MSTC signal is immediately changed to High.
(= “1”), and in the case of the IO module 91B, the slot number is odd (in the example shown, SLT0 = “1”, S
Since LT1 = "0"), after 100 ms, * MST
The C signal is set to High (= "1").

After the power is turned on, the reset signal * RST
IO modules 91A and 9A until the release (= “1”) of
The time difference between 1B was within 20 ms. It is assumed that the watchdog timer has not overflown. Thus, from the time chart of FIG.
It can be understood from the time difference for outputting the STC signal that the IO module mounted in the even-numbered slot always operates when the power is turned on. Next, a time chart when the IO module pair switches between operation and standby is shown in FIG.

FIG. 10 shows an example of switching between operation and standby by controlling the * MSTC signal. 8 and 10, when the * MSTC signal is inverted to L in the IO module 91A, the MSTS output from the JK FF 112A
The signal also becomes L, and is input to the NAND gate 114A to invert the signal D to H. Signal D is connected to connector 1
The signal is sent to the connection connector 120B of the other IO module 91B via 20A. Next, the M / S signal in the IO module 91B to which the signal D has been input is inverted to the H level, and input to the microprocessor 102B (the input line for the M / S signal is not shown), and
The module 91B is switched to the operating state.

In the IO module 91A, the signal D
Is inverted to H, the M / S signal is inverted to L level, and input to the microprocessor 102A (M / S
The signal input line is not shown), and is switched to a standby state. The same applies to the case of the * WDTE signal. However, in the case of the * WDTE signal, switching between operation and standby is directly performed by hardware without involving the microprocessor. Such an operation / standby switching circuit can be used for setting whether the IO module is used singly or redundantly. That is, the connection is made between the operation / standby switching circuits of the IO module pair, and the connection is made redundant.

During operation in such a state, any one of I
When the O module fails, for example, the operation display LED of the right module of the IO module pair is turned on. This state does not change even after the failed module is replaced with a non-defective one. This state is a state where there is no abnormality in the system, but when both the IO module pairs are normal, the operation display LED of the left module is displayed.
If is set so that is always lit, it is easy to confirm when maintaining the system. This is in order to respond to a user request to intentionally switch between operation and standby after replacing the faulty module with a non-defective one.

FIG. 11 shows a specific example. That is, I
One switch SW is provided on the O shelf 61 and connected to a processor (not shown) in the transmission control modules 7A and 7B via a connector mounted on the transmission control modules 7A and 7B on the IO shelf 61. This switch S
When W is operated, the processors of the transmission control modules 7A, 7B recognize this, and transmit an operation / standby switching command to the IO modules 91A, 91B to 98A, 98B via the IO buses 8A, 8B. At this time, the switch operation is performed for both the transmission control modules 7A and 7B
Of the IO module 91
Only the active transmission control module sends commands to A, 91B to 98A, 98B.

The active transmission control module senses the status of the IO module pairs in all slots via the IO bus, and operates the IO module pair of the IO module pair that is in the left standby state and the right operating state in the IO module pair. A command to switch from operation to standby is transmitted to the IO module. The IO modules 91B to 98B that have received the command to switch from operation to standby control the * MSTC signal to switch between operation and standby.

[0019]

However, the proposed method as described above, particularly the one shown in FIG. 11, not only significantly increases the load on the transmission control modules 7A and 7B, but also increases the IO bus occupancy. The problem remains that the performance of the system is degraded. Therefore, an object of the present invention is to reduce the load on the transmission control module and reduce the bus occupancy.

[0020]

In order to solve such a problem, according to the present invention, a transmission control module redundantly connected to a control unit is provided with a circuit having the same configuration having an operation / standby switching circuit. In a process input / output device in which a plurality of pairs of IO modules connected to a process are connected via an IO bus, a switch for transmitting an operation / standby switching command to each of the IO modules via a common signal line is provided. The operation / standby switching command is detected for each IO module, and the operation / standby between the paired IO modules can be switched for each process input / output device.

[0021]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention, and FIG. 2 is a detailed configuration example diagram of FIG. As is clear from FIGS. 1 and 2, this example is based on the IO bus 8A,
It is characterized in that an operation / standby switching command issued from the switch SW is directly given to the processor of each of the IO modules 91A, 91B to 98A, 98B via a common signal line CH different from 8B. Is similar to the proposed method. Therefore, when the switch SW is operated, the processors of the active / standby IO modules recognize this, and if the IO module in the right slot in the IO module pair is active, the IO module is set to the * MSTC Switching between operation and standby by controlling the signal.

In this case, as shown in FIG. 2, * MSTC
The IO module that controls the signal can sense the duplex setting and the operation / standby switching signal D using the input port of the processor, and as described with reference to FIG.
Check that the IO module on the standby side enters the operating state. If it does not enter the operating state (the signal D remains High), it determines that the partner module has failed or that the partner module has not been mounted, and stops the operation / standby switching.
As described above, a signal line CH different from the data transmission buses of the IO buses 8A and 8B is provided, and operation /
Since the standby switching command is directly given to the processor of each IO module, the occupancy of the IO bus can be kept low, and the load on the transmission control module can be greatly reduced. As a result, operation during switch operation /
The performance of the system is not degraded during the standby switching operation.

[0023]

According to the present invention, an operation / standby switching command is not directly given to the transmission control module connected to the data transmission bus, so that the following effects can be expected. a) The load on the transmission control module is significantly reduced. b) IO bus occupancy can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention.

FIG. 2 is a detailed configuration example diagram of FIG. 1;

FIG. 3 is a general schematic configuration diagram of a distributed control system.

FIG. 4 is an enlarged view of a main part of FIG. 3;

FIG. 5 is a configuration diagram showing a conventional example.

FIG. 6 is an enlarged view of a main part of FIG. 5;

FIG. 7 is a configuration diagram showing a proposed method.

FIG. 8 is a detailed configuration example diagram of FIG. 3;

FIG. 9 is a diagram illustrating a first operation in FIG. 3;

FIG. 10 is an explanatory diagram of a second operation in FIG. 3;

FIG. 11 is a configuration diagram showing another modification of the proposed method.

[Explanation of symbols]

4A: Control MPU, 5A, 5B: IO link, 61: I
O shelf, 7A, 7B ... transmission control module, 8A,
8B: IO bus, 91A, 91B to 98A, 98B: I
O module, 102A, 102B: microprocessor, D: duplex setting and operation / standby switch signal, SW: operation / standby switch, CH: signal line.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5H209 AA01 BB01 CC01 CC13 DD02 DD11 GG02 GG11 SS01 SS04 SS08 TT01 5H215 AA01 BB11 CC03 CX05 GG02 KK03

Claims (1)

[Claims] 1. A transmission control module redundantly connected to a control unit is paired with an identically configured circuit having an operation / standby switching circuit, and a plurality of pairs of IO modules connected to a process are connected via an IO bus. In the connected process input / output device, a switch for transmitting an operation / standby switching command to each of the IO modules via a common signal line is provided, and the operation / standby switching command is detected for each IO module. A duplex configuration of a process input / output device, wherein operation / standby between a pair of IO modules can be switched for each process input / output device.