JPS5471910A - Electronic exchange - Google Patents

Electronic exchange

Info

Publication number
JPS5471910A
JPS5471910A JP13843977A JP13843977A JPS5471910A JP S5471910 A JPS5471910 A JP S5471910A JP 13843977 A JP13843977 A JP 13843977A JP 13843977 A JP13843977 A JP 13843977A JP S5471910 A JPS5471910 A JP S5471910A
Authority
JP
Japan
Prior art keywords
memory
write
processors
function
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13843977A
Other languages
Japanese (ja)
Other versions
JPS5651716B2 (en
Inventor
Toshihiro Arima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13843977A priority Critical patent/JPS5471910A/en
Publication of JPS5471910A publication Critical patent/JPS5471910A/en
Publication of JPS5651716B2 publication Critical patent/JPS5651716B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To make it possible to process unificatively the rewrite of conversion information to the main memory of each processor by providing a bus for signals which controls plural processors. CONSTITUTION:Each of processors 45, 55, 65 and 80 connected through processor bus 90 is constituted by central processing unit 555, memory protect circuit 556, main memory 557, processor bus connection circuit 554, etc., and memory 557 has a write-protected area at a normal operation time, and circuit 556 has a function to prevent unit 555 from operating the write to the write-protected area. Then, when one of these processors is assigned by busses 93 and 97 for signals, the memory protect function is released in 555 to operate the release function in a prescribed time, and further, the selection of permission or inpermission for operating busses 93 and 97 can be controlled by a switch of system monitor unit 71.
JP13843977A 1977-11-19 1977-11-19 Electronic exchange Granted JPS5471910A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13843977A JPS5471910A (en) 1977-11-19 1977-11-19 Electronic exchange

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13843977A JPS5471910A (en) 1977-11-19 1977-11-19 Electronic exchange

Publications (2)

Publication Number Publication Date
JPS5471910A true JPS5471910A (en) 1979-06-08
JPS5651716B2 JPS5651716B2 (en) 1981-12-07

Family

ID=15222003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13843977A Granted JPS5471910A (en) 1977-11-19 1977-11-19 Electronic exchange

Country Status (1)

Country Link
JP (1) JPS5471910A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5963895A (en) * 1982-10-04 1984-04-11 Nec Corp Control method of information

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63242819A (en) * 1987-03-30 1988-10-07 Kyoto Seisakusho:Kk Method of standing article upright and device therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5963895A (en) * 1982-10-04 1984-04-11 Nec Corp Control method of information
JPH0417496B2 (en) * 1982-10-04 1992-03-26 Nippon Electric Co

Also Published As

Publication number Publication date
JPS5651716B2 (en) 1981-12-07

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