EP1889287A1 - Procede de traitement ultraviolet pour des materiaux dielectriques appliques par centrifugation utilises dans des applications d'isolation premetalliques et/ou de tranchees peu profondes - Google Patents

Procede de traitement ultraviolet pour des materiaux dielectriques appliques par centrifugation utilises dans des applications d'isolation premetalliques et/ou de tranchees peu profondes

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Publication number
EP1889287A1
EP1889287A1 EP05769209A EP05769209A EP1889287A1 EP 1889287 A1 EP1889287 A1 EP 1889287A1 EP 05769209 A EP05769209 A EP 05769209A EP 05769209 A EP05769209 A EP 05769209A EP 1889287 A1 EP1889287 A1 EP 1889287A1
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EP
European Patent Office
Prior art keywords
dielectric material
spin
metal
ultraviolet radiation
exposing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP05769209A
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German (de)
English (en)
Inventor
Carlo Waldfried
Orlando Escorcia
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Axcelis Technologies Inc
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Axcelis Technologies Inc
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Publication date
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Publication of EP1889287A1 publication Critical patent/EP1889287A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/075—Silicon-containing compounds
    • G03F7/0757—Macromolecular compounds containing Si-O, Si-C or Si-N bonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating

Definitions

  • the present disclosure generally relates to dielectric films in semiconductor devices, and more particularly, to ultraviolet (UV) curing processes for spin-on low k dielectric films used in pre-metal and shallow trench isolation applications.
  • UV ultraviolet
  • the dimensions of the devices and spacings formed continue to be decreased so as to improve integrated circuit performance. Fabrication often requires the deposition of dielectric materials into features patterned into layers of material on silicon substrates. In most cases, it is important that the dielectric material completely fill such features without formation of any voids. Filling such narrow features, which is also referred to as gap filling, places stringent requirements on materials used, for example, the dielectric material used for pre-metal dielectric (PMD) or shallow trench isolation (STI) applications.
  • PMD pre-metal dielectric
  • STI shallow trench isolation
  • the aspect ratio required to be filled by the pre-metal dielectric material may be as high as 16:1 for DRAM devices in the year 2005, which translates to depths greater than 300 nanometers (nm).
  • the dielectric materials need to be able to withstand subsequent processing steps, such as high temperature annealing, etching, and cleaning steps.
  • the dielectric materials employed for PMD and STI applications are generally deposited by chemical vapor deposition or by spin-on processes. Each of these approaches has some limitations for filling very narrow gaps that will need to be overcome for successful integration.
  • Spin-on glasses and spin-on polymers such as silicates, siloxanes, silazanes or silisequioxanes generally have good gap-fill properties.
  • the films of these materials are typically formed by applying a coating solution containing the polymer followed by a thermal cure process.
  • the thermal cure process is generally performed to complete the formation of chemical bonds, outgas residual components, and reduce the dielectric constant in the film.
  • This curing process is commonly performed in a furnace using a batch mode or on a hotplate utilizing a single wafer mode. In either case, the conventional cure process undesirably subjects the wafer to an elevated temperature for an extended period of time (e.g., in excess of one hour to several hours and at a temperature in greater than about 300° C).
  • a UV curing process for a dielectric material used in pre-metal and shallow trench isolation applications comprises coating a dielectric material onto a substrate; and exposing the dielectric material to ultraviolet radiation in an amount effective to reduce an organic content in the dielectric material.
  • a UV curing process for a dielectric material used in pre-metal and shallow trench isolation applications comprises coating a dielectric material onto a substrate; and exposing the dielectric material to ultraviolet radiation in an amount effective to densify the dielectric material.
  • a UV curing process for a dielectric material used in pre-metal and shallow trench isolation applications comprises coating a dielectric material onto a substrate; and exposing the dielectric material to ultraviolet radiation in an amount effective to increase a wet etch resistance of the dielectric material , wherein the wet etch resistance increases relative to a wet etching rate of the dielectric material prior to the exposure.
  • a process for curing a spin on pre-metal dielectric material coated onto a surface of a substrate comprises coating a spin on pre-metal dielectric material onto a substrate; exposing the spin on pre-metal dielectric material to a first ultraviolet radiation pattern for a period of time and intensity effective to increase an elastic modulus property and/or a hardness property of the pre-metal dielectric material; and exposing the spin on pre-metal dielectric material to a second ultraviolet radiation pattern for a period of time and intensity effective to further increase the elastic modulus property and/or the hardness property of the pre-metal dielectric material, wherein the first and second ultraviolet radiation patterns are different.
  • Figure 1 graphically illustrates the broadband spectral output of a Type
  • I electrodeless microwave driven bulbs from Axcelis Technologies, Inc., respectively, which is suitably used for UV curing the dielectric materials;
  • Figure 2 graphically illustrates the broadband spectral output of a Type
  • Figure 3 graphically illustrates FTIR spectra for a pre-metal dielectric film that was uncured and UV cured in accordance with one embodiment
  • FIGS 4-5 are charts illustrating wet etch resistance in various dilute hydrofluoric acid solutions (DHF) or non-UV cured and UV cured spin low k dielectric materials compared to a TEOS dielectric deposited by chemical vapor deposition;
  • DHF dilute hydrofluoric acid solutions
  • Figures 6-7 are charts illustrating wet etch resistance as a function of time in various dilute hydrofluoric acid solutions for non-UV cured and UV cured spin low k dielectric materials compared to a TEOS dielectric deposited by chemical vapor deposition;
  • Figure 8 is a chart illustrating dielectric constant for spin on pre-metal low k dielectric materials before and after UV exposure, wherein the process chamber employed different inert gases;
  • Figure 9 is a chart illustrating breakdown voltages for spin on pre-metal low k dielectric materials before and after UV exposure, wherein the process chamber employed different inert gases.
  • the present disclosure is directed to a UV curing process for spin-on pre-metal dielectric materials.
  • pre-metal dielectric is intended to include shallow trench dielectric applications, since these dielectric materials are generally the same and optimized for gap filling. Applying the UV cure process described herein will have similar advantages for both PMD and STI applications.
  • the UV curing process generally includes spin coating the pre- metal dielectric material onto a suitable substrate prior to depositing any metal layers in the integrated circuit and exposing the dielectric material to ultraviolet radiation having one or more wavelengths greater than 150 nanometers to less than 400 nanometers at a temperature less than about 45O 0 C.
  • the UV cure process removes organic-like impurities or moieties that may have been formed in the spin-on pre-metal dielectric material.
  • spin-on dielectric material includes, but is not intended to be limited to, silicates, hydrogen silsesquioxanes, organosilsesquioxanes, organosiloxanes, organhydridosiloxanes, silsesquioxane-silicate copolymers, silazane-based materials, polycarbosilanes, and acetoxysilanes.
  • the UV curing process removes and/or chemically modifies a portion of the dielectric material.
  • the UV curing process advantageously increases the density of the dielectric material, and/or reduces the organic content, and/or increases the wet etch resistance of the dielectric material.
  • the monomers, monomer mixtures and polymers described herein for forming the spin-on pre-metal dielectric material can be and in many ways are designed to be solvated or dissolved in any suitable solvent, so long as the resulting solutions can be spin coated or otherwise mechanically layered on to a substrate, a wafer, or a layered material.
  • Preferred solutions are designed and contemplated to be spin coated, rolled, dripped or sprayed onto a wafer, a substrate, or the layered material.
  • Most preferred solutions are designed to be spin coated onto a wafer, a substrate or layered material.
  • Typical solvents are those solvents that are readily available to those in the field of dielectric materials, layered components, or electronic components.
  • Typical solvents are also those solvents that are able to solvate the monomers, isomeric monomer mixtures and polymers.
  • Contemplated solvents include any suitable pure or mixture of organic, organometallic or inorganic molecules that are volatilized at a desired temperature.
  • the solvent may also comprise any suitable pure or mixture of polar and non- polar compounds.
  • the solvent comprises water, ethanol, propanol, acetone, toluene, ethers, cyclohexanone, butyrolactone, methylethylketone, methylisobutylketone, N- methylpyrrolidone, polyethyleneglycohnethylether, mesitylene, and anisole.
  • the UV curing process comprises spin coating a suitable pre-metal dielectric material onto a substrate, and exposing the pre-metal dielectric material to an ultraviolet radiation pattern at a temperature less than about 45O 0 C for a period of time effective to increase the density and/or increase the wet etch resistance and/or decrease the organic content in the dielectric material.
  • a spin-on dielectric material there are numerous methods of coating a spin-on dielectric material as is known in the art, and all of the known methods are considered appropriate.
  • Suitable substrates contemplated herein may comprise any desirable substantially solid material for which a pre-metal dielectric or shallow trench isolation structure including the spin-on dielectric material may be desired.
  • suitable substrates include, but are not limited to, silicon, silicon dioxide, glass, silicon nitride, ceramics, and gallium arsenide.
  • the term substrates also generally refers to any of the layers, planarized or having topography, including, semiconducting wafers, dielectric layers, gates, barrier layers, etch stop layers, and metal lines found in integrated circuit devices.
  • an annealing process may be employed after the UV cure process.
  • the annealing processes can comprise exposing the substrate containing the UV cured pre-metal dielectric material to an elevated temperature for a period of time effective to increase the density and/or increase the wet etch resistance and/or decrease the organic content in the dielectric material.
  • the annealing temperature may be up to about 1,100 0 C for about 2 hours or less.
  • the resulting UV cured pre-metal dielectric material has been found to be more stable to a subsequent wet chemical treatment processes, such as is commonly employed during the integrated circuit fabrication process.
  • a wet etching process may be employed to selectively remove portions of the substrate and/or deposited layers.
  • the substrate is immersed into a stripper such as a dilute aqueous hydrofluoric acid bath.
  • a stripper such as a dilute aqueous hydrofluoric acid bath.
  • Other wet strippers include acids, bases, and solvents as are known to those skilled in the art.
  • the particular wet strippers used are well within the skill of those in the art. For example, nitric acid, sulfuric acid, ammonia, hydrofluoric acid are commonly employed as wet strippers.
  • the wet stripper is immersed, puddled, streamed, sprayed, or the like onto the substrate and subsequently rinsed with deionized water.
  • the UV cured spin on dielectric material has improved wet etch resistance relative to the same material that was not exposed to the UV cure process.
  • a UV irradiator tool is utilized.
  • a suitable UV irradiator tool is the RapidCureTM tool commercially available from Axcelis Technologies, Incorporated.
  • the light source chamber may be purged with an inert gas such as nitrogen, helium, or argon to allow the UV radiation to enter an adjacent process chamber with minimal spectral absorption.
  • the pre-metal dielectric material is positioned within the process chamber, which is purged separately and process gases, such as N 2 , H 2 , Ar, He, Ne, H 2 O vapor, CO 2 , O z , C x H y , C x F y , C x H 2 F y , and mixtures thereof, wherein x is an integer between 1 and 6, y is an integer between 4 and 14, and z is an integer between 1 and 3, may be utilized for different applications.
  • process gases such as N 2 , H 2 , Ar, He, Ne, H 2 O vapor, CO 2 , O z , C x H y , C x F y , C x H 2 F y , and mixtures thereof, wherein x is an integer between 1 and 6, y is an integer between 4 and 14, and z is an integer between 1 and 3, may be utilized for different applications.
  • UV curing can occur at vacuum conditions, or at conditions without the presence of oxygen, or with oxidizing gases
  • the UV light source can be microwave driven, arc discharge, dielectric barrier discharge, or electron impact generated.
  • UV generating bulbs with different spectral distributions may be selected depending on the application such as, for example, microwave electrodeless bulbs identified as Type I or Type II and available from Axcelis Technologies (Beverly, MA). Spectra obtained from the Type I and Type II bulbs and suitable for use in the UV cure process are shown in Figures 1 and 2, respectively.
  • the substrate (wafer) temperature may be controlled ranging from room temperature to 450 0 C, optionally by an infrared light source, an optical light source, a hot surface, or the light source itself.
  • the process pressure can be less than, greater than, or equal to atmospheric pressure.
  • the UV cured dielectric material is UV treated for no more than or about 600 seconds, and preferably no more than about 300 seconds and, more particularly, between about 60 and about 180 seconds.
  • UV treating the dielectric material can be performed at a temperature between about room temperature and about 450 0 C; at a process pressure that is less than, greater than, or about equal to atmospheric pressure; at a UV power between about 0.1 and about 2,000 mW/cm 2 ; and a UV wavelength spectrum between about 100 and about 400nm.
  • a pre-metal dielectric material identified as Honeywell Electronic Material A (HEMA) and obtained from Honeywell Company was spin coated onto bare silicon wafers.
  • the wafers were subjected to a conventional spin process recommended by the manufacturer. Each wafer was processed identically.
  • the coated wafers were exposed to a UV cure process at 425 0 C for a period of 5 minutes.
  • the UV cure process employed various microwave electrodeless bulbs in a Rapid Cure Exposure tool commercially available from Axcelis Technologies, Incorporated.
  • FTIR data as shown in Figure 3 did not show any detectable absorbance changes in the low k dielectric material after the UV cure.
  • the UV cured wafers were then exposed to a wet etching process that comprised immersing the wafers in a 40:1 and a 100:1 dilute hydrofluoric acid aqueous based solution for 2 minutes, 5 minutes, and 10 minutes.
  • the above ratio represents the amount by weight of water to hydrofluoric acid.
  • the results are shown in Figures 4, 5 and are shown relative to a tetraorthosilicate (TEOS) films deposited using plasma enhanced chemical vapor deposition (PECVD), which is generally known for its wet etch resistance but is unsuitable for use as a pre-metal dielectric material for advanced design rules, e.g., less than 90 nanometers.
  • TEOS tetraorthosilicate
  • PECVD plasma enhanced chemical vapor deposition
  • the UV cure process clearly reduced the pre-metal dielectric wet etch resistance in the 40: 1 hydrofluoric acid solution.
  • the etching rate was about 820 angstroms/minute for the uncured material, which was reduced to as much as about 350 angstroms/minute depending on the composition of the pre-metal dielectric material.
  • the time variable had minimal effect. Comparable results were observed in the more dilute HF solution (100:1). However, the results were less visibly dramatic due to the relatively weak etching behavior observed as a result of the dilution.
  • the HEMA pre-metal spin-on dielectric material was spin coated onto blank wafers as in Example 1.
  • a nanoglass spin on dielectric material available from the Honeywell Corporation under the identifier NGX was spin coated onto blank wafers.
  • the wafers were exposed to UV radiation produced in the RapidCure tool utilizing a Type III electrodeless bulb at 425 0 C for 10 minutes in an inert gas mixture.
  • the thickness and the refractive index (RI) after the spin on dielectric was post baked and after the UV cure process were measured.
  • Some of the wafers were further exposed to a furnace anneal process at 900 0 C or 1000 0 C for 1 hour.
  • wafer set number 1 refers to the HEMA spin coated dielectric materials
  • wafer set numbers 2 and 3 refer to the spin coated NGX low k dielectric materials, wherein each wafer set represents the average of three processed wafers.
  • Table 1 The data is presented in Table 1.
  • PB refers to the dielectric material after a spin coating and post bake process
  • PC refers to the PB dielectric after UV curing
  • PA refers to the dielectric after PB and PC and exposure to a furnace anneal process.
  • Example 3 the dielectric constant and breakdown voltage was measured before and after the UV cure process as in Example 1.
  • Spin low k dielectrics identified as HEMA (ml), (m2), and (m3) were coated using a conventional spin coat process as recommended by the manufacturer for the particular low k dielectric. The results are shown in Table 3 below.
  • exposing the spin-on dielectric material to the UV cure process advantageously decreased the dielectric constant. Along with the decrease in dielectric constant a concomitant increase in breakdown voltage was observed.
  • NR(I) refers to the use of helium as the inert gas whereas NR(2) refers to the use of a hydrogen/helium gas mixture.
  • Figures 8 and 9 graphically illustrate dielectric constant and breakdown voltage for the respective films. The UV cure process significantly improves dielectric constant and breakdown voltage.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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  • Element Separation (AREA)

Abstract

Le procédé de traitement aux UV selon l'invention pour un matériau diélectrique utilisé dans les applications d'isolation prémétalliques et de tranchées peu profondes comprend l'application d'un matériau diélectrique adapté sur un substrat; et l'exposition du matériau diélectrique à une radiation ultraviolette dans une proportion efficace pour réduire la teneur organique et/ou augmenter la densité et/ou réduire la résistance à la gravure humide du matériau diélectrique. Optionnellement le matériau diélectrique traité aux UV peut être exposé à des configurations de radiations ultraviolettes multiples.
EP05769209A 2005-06-09 2005-06-09 Procede de traitement ultraviolet pour des materiaux dielectriques appliques par centrifugation utilises dans des applications d'isolation premetalliques et/ou de tranchees peu profondes Withdrawn EP1889287A1 (fr)

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