EP1393370A2 - Elektronischer chip und elektronische chip-anordnung - Google Patents
Elektronischer chip und elektronische chip-anordnungInfo
- Publication number
- EP1393370A2 EP1393370A2 EP02748564A EP02748564A EP1393370A2 EP 1393370 A2 EP1393370 A2 EP 1393370A2 EP 02748564 A EP02748564 A EP 02748564A EP 02748564 A EP02748564 A EP 02748564A EP 1393370 A2 EP1393370 A2 EP 1393370A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- chip
- electronic
- electronic chip
- external
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
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- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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Definitions
- the invention relates to an electronic chip and an electronic chip arrangement.
- the chip arrangement 200 has a first electronic chip 201 and a second electronic chip 202, the first chip 201 and the second chip 202 having to be contacted electrically.
- the first chip 201 has a plurality of electrical components, an electrical resistor 204, a capacitance 205 and an inductor 206, which are integrated as electrical circuit 207 in the first electronic chip 201.
- the first chip has a first external chip
- Metal contact 208 via which the first electronic chip 201 is electronically coupled to the second electronic chip 202.
- the second chip 202 also has an electrical one
- Circuit on (not shown), which is integrated in the second chip 202. Furthermore, a is in the second chip 202 second external chip metal contact 209 is provided, which is used for electrical contacting with the first electronic chip metal contact 208 of the first electronic chip 201.
- solder material 210 is introduced for the electronic coupling of the two chip metal contacts 208, 209.
- the two external chip metal contacts 208, 209 are coupled by means of the solder material 210, preferably by soldering the chip metal contacts 208, 209 to the solder material 210.
- BGA ball grid array method
- FC flip chip method
- FSC chip scale packaging method
- PDIP plastic dual -In-line packages process
- QFP Quad Fiat Packs process
- SOICs Small Outline ICs process
- the external chip-metal contacts are soldered to one another or contacted by means of bonding wires, or at least by means of metal connections.
- the limited current carrying capacity of the connecting material is disadvantageous, in particular in the case of a high-frequency application, since it results in very strong heating and a not insignificant electronic resistance of the chip coupling.
- cracks generally damage in the metal connection, can occur in the coupling itself due to the considerable mechanical load, which can lead to deteriorated electronic contacting or even to no longer existing electronic contacting.
- [1] also discloses a tactile sensor in which a large number of nanowires are grown on a plurality of contact elements. An element to be detected by means of the sensor is detected in that the nanowires are mechanically bent by that of the element, so that the nanowires touch adjacent contact elements of the sensor and an electrical short circuit is thus formed.
- [2] describes a microelectronic device in which a nanoporous layer is introduced between two electrically conductive contacting elements, the pores being filled with metal, so that the contacting elements are electrically coupled by means of the metal-filled pores.
- [3] describes a process for the production of carbon nanotubes.
- the invention is therefore based on the problem of electronically conducting coupling of an electronic chip to an additional chip via an external electronic chip contact, the coupling being designed to be less susceptible to faults.
- An electronic chip has a plurality of external chip contacts, preferably a plurality of chip metal contacts, on each of which a plurality of nanotubes are applied for contacting the electronic chip with another electronic chip.
- the other electronic chip also has a plurality of external chip contacts, preferably a plurality of chip metal contacts.
- the multiplicity of nanotubes each of an external chip contact are to be contacted with a corresponding, clearly associated, external chip contact of the other electronic chip.
- an electronic chip is to be understood as a normally finished electronic chip.
- fully processed means that all process steps for the production of electrical circuits integrated in the chip have been completed and only possible packaging steps (packaging process steps) with the appropriate attachment of housings have not yet been carried out.
- an external chip contact means an electrical contact of the chip which is still present after the chip has been finished, for external control of the chip, i.e. by a control or a signal exchange from an element located in the vicinity of the chip, for example with another chip.
- An electronic chip arrangement has a first electronic chip and a second electronic chip.
- the first electronic chip has a plurality of external chip contacts, on which a plurality of nanotubes are applied for contacting the electronic first chip with the second electronic chip.
- the second electronic chip also has a plurality of external chip contacts which can be electrically and mechanically contacted with the nanotubes applied to the first chip contact of the first electronic chip.
- the nanotubes of an external chip contact of the first electronic chip are contacted with exactly one external chip contact of the second external chip contact.
- nanotubes preferably carbon nanotubes
- the use of nanotubes according to the invention has the particular advantage that the nanotubes used are flexible and that there is therefore a more stable coupling both with regard to the mechanical stability and with regard to the reliability of the electronic coupling between the external ones Chip contacts is achieved. This is particularly due to the fact that the modulus of elasticity is approximately one TPa.
- Another advantage of the coupling between the electronic chips according to the invention is that the nanotubes are chemically inert.
- Carbon nanotubes are usually used, the current carrying capacity, in particular of the electrically conductive carbon nanotubes, being up to a factor of 1000 greater than, for example, the current carrying capacity of copper as the metal usually used for the connection between two electronic chips.
- Another advantage is the thermal conductivity of the nanotubes, which is around 6000 watts / mK, whereas the thermal conductivity of copper is about 400 watts / mK.
- nanotubes especially carbon nanotubes
- the use of nanotubes, especially carbon nanotubes reduces the problem described above in two ways.
- the high thermal conductivity of the nanotubes quickly dissipates the heat to the environment;
- the shear forces that occur in the coupling due to the easily movable and yet stable nanotubes can be reduced without the nanotubes themselves being destroyed.
- the nanotubes can be configured as carbon nanotubes, in this connection in particular as electrically conductive or electrically semiconducting carbon nanotubes.
- the chip contact which preferably consists of metal and is henceforth also referred to as chip-metal contact, can consist of a layer sequence, in particular two layers, a chip-metal contact layer and a catalyst layer applied thereon.
- the catalyst layer has material which has a catalytic effect with regard to the growth of nanotubes, preferably with regard to the growth of carbon nanotubes.
- a catalyst layer is also to be understood as an accumulation of individual material clusters from the respective catalyst material, the catalyst layer does not necessarily have to consist of a continuous layer of catalyst material.
- the chip metal contact layer itself can also consist of a metal which has a catalytic effect with regard to the growth of the nanotubes.
- the growth of the nanotubes is considerably simplified and accelerated by the use of catalyst material.
- the chip-metal contact in particular the chip-metal contact layer, can be made from any metal, preferably from aluminum and / or copper or from any metal alloy, preferably from a metal alloy of the two metals mentioned above.
- Nickel, cobalt or iron or a mixture of the materials mentioned can be used as the catalyst material.
- the nanotubes are soldered to the external chip metal contact in order to improve the mechanical contact, i. the mechanical coupling between the external chip contact and one end of a respective nanotube to further strengthen, whereby the mechanical stability of the chip connection is further increased.
- the mechanical coupling between an external chip contact and one end of a respective nanotube can be implemented by means of an electrochemical coupling.
- the electronic chip is designed as a test chip, ie as a chip with which a given functionality of further electronic chips can be tested.
- the nanotubes clearly serve as a replacement for the usual needle card for contacting the chip to be tested in each case.
- the test chip can have an integrated test circuit, which further increases the reliability of the processed electrical signals.
- the nanotubes can be soldered to the metal of the respective external chip contacts at their two respective ends be, whereby the mechanical and thus also the electronic stability is further increased.
- the invention can be applied to any number of electronic chips to be contacted.
- the invention is particularly suitable for use in an RF application, i.e. with high-frequency components or in a high-frequency chip.
- FIG. 1 shows an electronic chip arrangement according to a first exemplary embodiment of the invention at a first point in time of the production process
- FIG. 2 shows an electronic chip arrangement according to the prior art
- FIG. 3 shows an electronic chip arrangement according to the first exemplary embodiment of the invention at a second point in time of the production method
- FIG. 4 shows an electronic chip arrangement according to the first exemplary embodiment of the invention at a third point in time of the production method
- FIG. 5 shows an electronic chip arrangement according to a second exemplary embodiment of the invention.
- Figure 6 is a scanning electron microscope image of a
- FIG. 1 shows a chip arrangement 100 according to a first exemplary embodiment of the invention at a first point in time during its manufacture.
- the chip arrangement 100 has a first electronic chip 101 and a second electronic chip 102, which are to be contacted mechanically and electronically with one another.
- the first electronic chip 101 and the second electronic chip 102 each have an integrated electronic circuit, which, however, are not shown for the sake of a simplified explanation of the invention.
- a catalyst layer 104 made of iron is applied on a contact pad, ie on an external chip metal contact 103 made of aluminum by means of a lift-off method, wherein according to this exemplary embodiment the catalyst layer 104 consists of a plurality arranged side by side Metal particles, especially metal clusters made of iron.
- the external chip metal contact 103 can be applied directly together with the catalyst material to the electronic chip 101, which is actually processed.
- the catalyst layer 104 has a thickness of approximately 5 nm to 10 nm.
- Embodiment grew up to a height of about 100 microns to 500 microns.
- the external chip metal contact 103 has a rectangular shape with a side length of 50 ⁇ m to 100 ⁇ m in each case.
- the carbon nanotubes 105 and thus the chip-metal contact 103 of the first electronic chip 101 are brought into local agreement and brought into mechanical contact with a chip-metal contact 106 of the second electronic chip 102, i. the carbon nanotubes 105 are adjusted with the chip metal contact 106 of the second electronic chip 102.
- the carbon nanotubes 105 are then embedded in the aluminum of the metal contact layer 103, ie the external chip contact 103, by heating the chip arrangement 100 using a short-time annealing process in a hydrogen environment at above 660 ° C. and then cooling it again.
- the carbon nanotubes 105 are firmly connected at a respective first end 107 to the aluminum of the external chip metal contact 103 of the first electronic chip 101, ie fastened in the aluminum, and then the first electronic chip 101 is placed over the desired contact area , ie the chip metal contact 106 of the second electronic chip 102, is adjusted and then again heated and cooled again by means of a short-term annealing process in a hydrogen environment at a temperature of over 660 ° C., so that the respective second ends 108 are firmly attached to the aluminum of the external chip metal contact 106 of the second electronic chip 102 connected, that is, fixed in the aluminum.
- the ends 107, 108 of the carbon nanotubes 105 are clearly soldered to the external chip metal contacts 103, 106.
- FIG 3 shows the state of the chip arrangement 100 after the first ends 107 of the carbon nanotubes 105 have been soldered to the chip metal contact 103 of the first electronic chip 101 when identical reference numerals are used for identical elements.
- soldering is done by following the
- the chip arrangement 100 is brought for a short period of time above the eutectic temperature of the material of the chip metal contacts 103, 106, in order to thus embed the carbon nanotubes 105 in the material of the chip metal contacts 103, 106 , This takes place in the same way for embedding the further ends 108 of the carbon nanotubes 105 in the chip metal contacts 106 of the second electronic chip 102.
- Carbon nanotubes 105 in the chip metal contacts 103, 106 can be aluminum or any other metal or Metal mixtures such as Pb40Sn60, Pb95Sn5 or any other eutectic mixture can be used to contact the carbon nanotubes 105.
- FIG. 4 shows the chip arrangement 100 in the state in which the second ends 108 of the carbon nanotubes 105 are already embedded in the external chip metal contact 106 of the second electronic chip 102, i.e. are soldered to it.
- FIG 5 shows an electronic chip arrangement 500 according to a second exemplary embodiment of the invention.
- a first electronic chip 501 is designed as a test chip 501 and is used for testing further electronic chips to be tested, shown in accordance with this exemplary embodiment using a chip 502 to be tested.
- the test chip 501 has a test circuit integrated in it (not shown) and at least one external chip metal contact 503, basically any number of chip metal contacts 503, which have the first ends 507 according to the method described above the catalyst layer 504 grown carbon nanotubes 505 are soldered.
- the test circuit integrated in the test chip 501 is set up in such a way that it can be used to check a predetermined desired functionality of the electronic chip 502 to be tested.
- the second ends 508 are not firmly soldered to the external chip metal contact 506 of the electronic chip 502 to be tested, but rather they are are brought into mechanical and thus electrical contact only with the external chip contact 506 of the chip 502 to be tested for test purposes in order to carry out the respective test routine for testing the electronic chip 502 to be tested.
- FIG. 6 shows an image of a scanning electron microscope from a top view of an electronic chip 600 with a plurality of square external chip metal contacts and carbon nanotubes applied thereon, which clearly form a cluster lawn made of carbon nanotubes on the respective chip metal contact.
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Mathematical Physics (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Carbon And Carbon Compounds (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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DE10127351A DE10127351A1 (de) | 2001-06-06 | 2001-06-06 | Elektronischer Chip und elektronische Chip-Anordnung |
DE10127351 | 2001-06-06 | ||
PCT/DE2002/002026 WO2002099845A2 (de) | 2001-06-06 | 2002-06-03 | Elektronischer chip und elektronische chip-anordnung |
Publications (1)
Publication Number | Publication Date |
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EP1393370A2 true EP1393370A2 (de) | 2004-03-03 |
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Application Number | Title | Priority Date | Filing Date |
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EP02748564A Ceased EP1393370A2 (de) | 2001-06-06 | 2002-06-03 | Elektronischer chip und elektronische chip-anordnung |
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US (1) | US7301779B2 (de) |
EP (1) | EP1393370A2 (de) |
JP (1) | JP2004528727A (de) |
KR (1) | KR100585209B1 (de) |
DE (1) | DE10127351A1 (de) |
TW (1) | TWI283917B (de) |
WO (1) | WO2002099845A2 (de) |
Families Citing this family (46)
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US6864571B2 (en) * | 2003-07-07 | 2005-03-08 | Gelcore Llc | Electronic devices and methods for making same using nanotube regions to assist in thermal heat-sinking |
DE102004005255B4 (de) * | 2004-02-03 | 2005-12-08 | Siemens Ag | Verfahren zum Anordnen einer Leitungsstruktur mit Nanoröhren auf einem Substrat |
US7327037B2 (en) * | 2004-04-01 | 2008-02-05 | Lucent Technologies Inc. | High density nanostructured interconnection |
US7776307B2 (en) * | 2004-09-16 | 2010-08-17 | Etamota Corporation | Concentric gate nanotube transistor devices |
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US7476982B2 (en) * | 2005-02-28 | 2009-01-13 | Regents Of The University Of California | Fabricated adhesive microstructures for making an electrical connection |
EP1761114A3 (de) * | 2005-08-31 | 2009-09-16 | Kabushiki Kaisha Toyota Jidoshokki | Leiterplatte |
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US7625817B2 (en) * | 2005-12-30 | 2009-12-01 | Intel Corporation | Method of fabricating a carbon nanotube interconnect structures |
US7453154B2 (en) * | 2006-03-29 | 2008-11-18 | Delphi Technologies, Inc. | Carbon nanotube via interconnect |
US7713858B2 (en) | 2006-03-31 | 2010-05-11 | Intel Corporation | Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same |
KR100741286B1 (ko) * | 2006-04-06 | 2007-07-23 | 오태성 | 탄소나노튜브 강화 복합범프와 이를 이용한 칩온글라스실장방법과 플립칩 실장방법 |
US7544546B2 (en) * | 2006-05-15 | 2009-06-09 | International Business Machines Corporation | Formation of carbon and semiconductor nanomaterials using molecular assemblies |
JP4744360B2 (ja) | 2006-05-22 | 2011-08-10 | 富士通株式会社 | 半導体装置 |
WO2008024885A2 (en) * | 2006-08-23 | 2008-02-28 | The Regents Of The University Of California | Symmetric, spatular attachments for enhanced adhesion of micro-and nano-fibers |
US7600667B2 (en) * | 2006-09-29 | 2009-10-13 | Intel Corporation | Method of assembling carbon nanotube reinforced solder caps |
FR2910175B1 (fr) * | 2006-12-19 | 2009-07-31 | Commissariat Energie Atomique | Structure de cathode pour ecran plat avec grille de refocalisation |
US8168495B1 (en) | 2006-12-29 | 2012-05-01 | Etamota Corporation | Carbon nanotube high frequency transistor technology |
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- 2002-06-03 JP JP2003502860A patent/JP2004528727A/ja active Pending
- 2002-06-03 WO PCT/DE2002/002026 patent/WO2002099845A2/de active Application Filing
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KR100585209B1 (ko) | 2006-05-30 |
US7301779B2 (en) | 2007-11-27 |
TWI283917B (en) | 2007-07-11 |
KR20040030653A (ko) | 2004-04-09 |
WO2002099845A3 (de) | 2003-08-21 |
DE10127351A1 (de) | 2002-12-19 |
US20040233649A1 (en) | 2004-11-25 |
WO2002099845A2 (de) | 2002-12-12 |
JP2004528727A (ja) | 2004-09-16 |
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