EP1295336A2 - Systemträger für halbleiterchips und elektronische bauteile sowie herstellungsverfahren für einen systemträger und für elektronische bauteile - Google Patents

Systemträger für halbleiterchips und elektronische bauteile sowie herstellungsverfahren für einen systemträger und für elektronische bauteile

Info

Publication number
EP1295336A2
EP1295336A2 EP01949240A EP01949240A EP1295336A2 EP 1295336 A2 EP1295336 A2 EP 1295336A2 EP 01949240 A EP01949240 A EP 01949240A EP 01949240 A EP01949240 A EP 01949240A EP 1295336 A2 EP1295336 A2 EP 1295336A2
Authority
EP
European Patent Office
Prior art keywords
external contact
contact elements
system carrier
rivet
base substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01949240A
Other languages
German (de)
English (en)
French (fr)
Inventor
Stefan Paulus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1295336A2 publication Critical patent/EP1295336A2/de
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Definitions

  • the invention relates to a system carrier for semiconductor chips and electronic components and methods for their production.
  • the system carrier has external contact elements which have a rivet-shaped cross section with a rivet head region, a rivet shaft region and a rivet base region, the rivet base region being fixed on a base substrate which holds the system carrier together while being fitted with semiconductor chips.
  • the base substrate has an electrically conductive surface.
  • This electrically conductive surface has the advantage that an electrical voltage can be applied to the electrically conductive surface in order to build up external contact elements on the base substrate.
  • Such an electrically conductive surface is achieved in one embodiment of the invention by a base substrate made of a metallic foil.
  • the base substrate can consist of a plastic film with a metallic coating.
  • Such a film with a metallic coating has the advantage that it can be separated relatively easily in further processing from the electronic components to be formed on the system carrier.
  • the plastic film has a carbon coating, as a result of which its surface becomes electrically conductive.
  • This embodiment has the advantage that such plastic films with a carbon coating both have a sufficiently electrically conductive surface due to the carbon coating and also increase the possibility of separating the base substrate of the system carrier during the further processing of the semiconductor chips to electronic components.
  • each component assembly area can have one Be equipped chip that can be positioned in a central chip carrier area of the assembly area.
  • Circular, elongated or square external contact elements with rivet-shaped cross section can be grouped around the chip carrier area at a defined distance from the central chip carrier area.
  • external contact elements are arranged at least partially in the chip carrier area, so that a semiconductor chip with bond bumps on the rivet head areas of the external contact elements can be bonded using flip-chip technology.
  • the bond bumps of a semiconductor chip can be soldered or glued directly onto the rivet head area of the external contact surfaces, the external contact elements being excellently anchored in the plastic compound due to their rivet-shaped cross section.
  • a further advantage of the rivet-shaped external contact elements on the system carrier according to the invention is that the external contact elements can be matched to the later use of the system carrier by means of different layers of metals and precious metals.
  • the external contact element on the system carrier is made of pure silver or a silver alloy.
  • the material silver has the advantage that it does not form an oxide coating that inhibits electrical conductivity, but rather a silver sulfite coating that is electrically conductive.
  • the external contact element on the system carrier is constructed from a gold / nickel / gold layer sequence.
  • This layer sequence has the advantage that the gold does not form a resistance-increasing oxide layer and the nickel layer is completely surrounded by gold, so that a long service life of the external contact elements is guaranteed.
  • an outer gold layer serve as an etch stop when separating a system carrier of components.
  • the external contact elements are constructed from a silver / copper / silver layer sequence.
  • This layer sequence is cheaper and, by using materials with an extremely low electrical resistance, has an advantage over external contact elements made of a layer sequence of gold / nickel / gold.
  • the system carrier has a metallic base in the chip carrier area, the height of which corresponds to the external contact elements and the area of which is adapted to the size of the semiconductor chip.
  • This base can be constructed from the same material as the external contact elements, so that it can be created simultaneously with the external contact elements.
  • the base also has the advantage that it can be soldered or glued to the underside of the semiconductor chip, which does not have an active circuit, and can therefore have a ground or ground contact for the entire electronic component to the outside.
  • the system carrier is used in a preferred embodiment of the invention for the production of electronic components.
  • the external contact elements can have a circular outline or can also form elongated or square external contact elements.
  • a method for producing a system carrier with external contact elements that have a rivet-shaped cross section has the following method steps:
  • This method has the advantage that external contact elements are formed on the system carrier, which have a rivet-shaped cross section and are firmly anchored in the plastic mass due to this cross section, so that this system carrier ensures that the external contact elements do not delaminate from the surrounding plastic during the further processing steps.
  • a closed insulating layer is first applied, and this is then structured into an electrically insulating layer using photoresist technology.
  • photoresist technology for example, unexposed areas of the photoresist are detached and thus electrically conductive surface areas of the base substrate are exposed.
  • the structured electrically insulating layer is applied by means of a screen printing method, the screen advantageously acting as a structuring mask, so that an insulating layer is formed only in those areas in which the screen is not masked.
  • an initially closed insulating layer on the base substrate can be structured through a mask using a sputtering technique.
  • This technique also known as the sputtering technique, is directed by highly accelerated Ions removed the closed insulating layer at the places where it is not protected by a mask.
  • This method has the advantage that extremely fine structures with extremely straight walls can be produced.
  • a closed insulating layer can be carried out on the base substrate by means of deposition from the gas phase.
  • Organic gases are used as gases, which decompose on the surface of an electrically conductive layer and form an insulating film on the surface.
  • an initially closed insulating layer can be structured through a mask using plasma etching technology.
  • the insulation layer underneath is removed through the mask, but chemical reactions accelerate the removal of the insulation layer down to the conductive surface of the base substrate during plasma etching.
  • a technology for structuring closed insulating layers that does completely without a mask is laser raster radiation, in which the insulating layer is vaporized by means of a scanning laser beam that draws the structures into the insulating layer under the influence of laser energy.
  • a conductive material is now applied to the exposed electrically conductive surface areas.
  • the material can consist entirely of a single alloy or it can also be applied in layers with a different material sequence. However, for the manufacture of the system carrier according to the invention it is necessary that a conductive material is deposited and this conductive material grows beyond the structured insulating layer. Only then can the rivet-shaped cross section according to the invention for the external contact elements result.
  • the application of a conductive material is carried out by means of galvanic deposition on the exposed electrically conductive surface areas until the deposited material has overgrown at the exposed locations to form a rivet head.
  • the conductive material can also be obtained by deposition from the gas phase, for example by decomposing an organometallic compound over the base substrate and the metal being deposited from this connection on the base substrate in the exposed electrically conductive surface areas.
  • Electroless electrodeposition has the advantage that no electrical voltage has to be applied to the system carrier. Rather, the system carrier is immersed in the deposition bath and pulled out with an electrolessly deposited metal layer. When the structured insulating layer is removed, the desired rivet-shaped cross sections are formed in the surface areas provided for the external contact elements.
  • a metal base can be formed in the chip carrier area of the system carrier at the same time with the external contact elements.
  • a metallic base has the advantage that, for example, the underside of the semiconductor chip can be contacted with it.
  • any geometrical structure can be deposited on the base substrate, which corresponds to the formation of External contact surface arrangements is used. After the metallic material has been applied, the structured electrically insulating layer is removed. This can be done wet-chemically using solvents or by dry ashing in a plasma.
  • the electronic component has a semiconductor chip whose contact surfaces are connected to external contact elements, the semiconductor chip being encapsulated with the external contact elements in a plastic compound as a housing and at least one external contact element having a rivet-shaped cross section with a rivet head region, a rivet shaft region and a rivet foot region has, wherein the external contact element is anchored with its rivet head area in the plastic mass.
  • the plastic mass encloses the rivet head area in such a way that the rivet shaft is arranged in a completely fixed manner in the plastic mass.
  • the contact surface of the external contact element is provided by the rivet foot region, which is kept free of plastic compound, so that its surface has a contact surface that is accessible from the outside.
  • the rivet foot area can be designed differently and is circular in its embodiment in one embodiment.
  • the outer con Elongated tact area and thus rectangular.
  • the cross section remains riveted.
  • An elongated external contact element can thus have a rectangular external contact surface in the plan, which is formed by the rivet foot, and additionally show a riveted external contact surface due to the rivet-shaped cross section in elevation.
  • the rivet-shaped external contact surface is arranged at right angles to the external contact surface of the rivet base region, the external contact surfaces of the electronic component being located in a further embodiment of the invention in the edge region of the housing made of plastic material.
  • Circular floor plans of the rivet foot are provided as external contact surfaces if, in a further embodiment, the contact surfaces of the semiconductor chip have bond bumps which are bonded directly to the rivet head area of the external contact elements.
  • Such rivet-shaped external contact elements with a circular plan are therefore arranged directly under the semiconductor chip, so that they can be connected to the bumps of the semiconductor chip.
  • the semiconductor chip with its active side, which has a semiconductor circuit is aligned with the external contact elements.
  • a method for producing an electronic component which has external contact elements with a rivet-shaped cross section is characterized by the following method steps: provision of a substrate carrier which has a predetermined arrangement of the external contact elements, application of a plurality of semiconductor chips on the substrate carrier,
  • the flanks of the grown rivet-shaped cross-sections are almost vertical in the rivet shank area and only taper by 2 - 6 ⁇ m at a height of 30 ⁇ m.
  • mushroom or rivet shapes are formed on the system carrier, which guarantee excellent anchoring of the contact connection elements in the plastic compound.
  • the external contact elements can be realized with a wide variety of materials and layer sequences. External contact elements made from pure silver or from pure silver alloys or from layer sequences of gold / nickel / gold or silver / copper / silver can be grown on the base substrate of the system carrier.
  • a separating layer can also be inserted between the base layer and the external contact elements, for example a silver or a gold layer, so that there is a very good etching stop if the base substrate has to be dissolved again by etching.
  • you can also use the components in a later Process step are separated from the base substrate by mechanical processes. Under certain circumstances, a wet chemical etching process can be omitted.
  • the system carrier for a large number of discrete electronic components is advantageously cast over a large area with a plastic mass of uniform thickness to form a plastic plate made of plastic film which has the base substrate on one side.
  • the base substrate Before being separated into electronic components, the base substrate is etched away from the plastic plate, and in the case of an etch stop layer on the external contact elements, this etch stop layer protects the external contact elements from etching and ends the etching process.
  • the plastic plate can be coated with an adhesive film before separation.
  • the sawing technique is used as the separation technique during singling-in.
  • connections are established between contact areas on the semiconductor chip and the external contact element by means of flip-chip technology via bond bumps which are bonded to the rivet head area of the external contact elements.
  • bond bumps which are bonded to the rivet head area of the external contact elements.
  • the external contact elements are arranged correspondingly below the semiconductor chip opposite the contact areas of the semiconductor chip. The simultaneous bonding of all bond bumps is then easily possible on the rivet head areas of the external contact elements.
  • connections between the contact surfaces of the semiconductor chip and the external contact elements are achieved by means of bond wire technology via bond wires.
  • the contact areas of the semiconductor chip are connected to the head region of the external contact elements via the bonding wires.
  • a metallic base can be deposited on the system carrier, onto which the semiconductor chip can be soldered or glued. This has the advantage on the one hand that the semiconductor chip is supported by a metallic base, and on the other hand the advantage that the semiconductor underside has a large-area external contact through the metallic base.
  • the separation of the electronic components depends essentially on the material of the base substrate that was used for the production of the external contact elements.
  • the components can be removed relatively easily without the film having to be dissolved.
  • the carbon layer residues only have to be removed from the electronic component by a simple post-treatment step, which can be done by plasma ashing when the method is carried out.
  • Another possibility when separating the electronic components from a metal-coated plastic film as the base substrate is to remove this plastic film and to etch the metal coating remaining on the component using wet chemical or dry etching. Only when the metal coating tion is removed from the component, the external contact elements are accessible.
  • FIGS. 1-5 show, on the basis of schematic cross sections, essential manufacturing steps of a system carrier of a first embodiment of the invention
  • FIG. 6 shows a schematic cross section through the system carrier of FIG. 5 with an applied semiconductor chip using flip-chip technology
  • FIG. 7 shows a schematic cross section through an electronic component according to a first embodiment of the invention
  • Figure 8 shows a schematic cross section through a
  • Figure 9 shows a schematic cross section through an electronic component according to a second embodiment of the invention
  • Figure 10 shows a schematic cross section through a
  • FIG. 11 shows a schematic cross section through an electronic component according to a third embodiment of the invention.
  • FIG. 1 shows a schematic cross section through a base substrate 11 of a system carrier 5 with an underside 28 and an upper side 29, at least the upper side 29 having an electrically conductive surface 12.
  • This electrically conductive surface 12 can become electrically conductive by coating a plastic film or plastic plate with carbon.
  • a metallic coated plastic plate or plastic film can be used as the base substrate 11 for a system carrier 5.
  • Polyimide, polypropylene or polyethylene can advantageously be used as plastic for a film, while synthetic resins are preferably used as plastic plates.
  • the base substrate is a metallic foil which has an electrically conductive surface 12 on both the underside 28 and on the top 29.
  • the material of this metallic foil of FIG. 1 is a copper alloy with a thickness between 50 ⁇ m and 200 ⁇ m.
  • the base substrate 11 gives the system carrier 5 stability and is only removed after the completion of the electronic components to be arranged and produced on the system carrier.
  • FIG. 2 is a schematic cross section through the base substrate 11 of the system carrier 5 with a closed insulating layer 21.
  • This insulating layer 21 can be a photoresist layer that can be structured photolithographically, or another plastic rail that can be
  • Etching technology is structured by a mask or by laser raster radiation.
  • FIG. 3 shows a schematic cross section through the base substrate 11 of the system carrier 5 of a first embodiment of the invention with a structured electrically insulating layer 18, in which embodiment the u> J tt P 1 P 1 tn o in o U1 o in ⁇ co w Hl ö P ) ⁇ - Hi) IQ ⁇ S ⁇ O rt ⁇ CQ ⁇ PJ O C ⁇ H ⁇ • fl CQ ⁇ i H os; ⁇ ⁇ N CQ CQ
  • P- P- c P Hi 3 h P ⁇ C CQ PMH? ⁇ H CQ tr ⁇ ⁇ P: rt ⁇ ⁇ ⁇ Q? t ⁇ rt PH P- P- 2 i HPWJ ⁇ IQ Hi ⁇ i ri O ⁇ rt CW P-
  • the rivet base area 10 different galvanic baths different material layer sequences for the rivet base area 10, the rivet shank area 9 and / or the rivet head area 8 can be realized.
  • a gold or silver layer can first be deposited in the rivet base region 19 in order to serve as an etching stop for the subsequent separation of the system carrier 5 before being separated into electronic components.
  • the electrically conductive surface 12 of the base substrate 11 or the entire base substrate is made of a base metal than the rivet base region 10 of the external contact elements 6.
  • Other external contact elements have a layer sequence of gold in the base region, nickel in the stem region and head region and a final gold coating on the Head area on.
  • the rivet shank region 9 can, however, also be made of the same material as the electrically conductive surface 12 and, in the transition to the rivet base region 10 of the external contact element, have a nobler separating layer which serves as an etching stop.
  • the base substrate 11 is produced from a copper alloy and the rivet shaft region 9 is likewise produced from a copper alloy and a silver layer is applied in between in the rivet base region 10.
  • electrically conductive material 20 to form external contact elements 6 with a rivet-shaped cross section 7 can also be carried out by metal deposition from the gas phase of organometallic compounds or by electroless deposition of metal ions from a liquid.
  • FIG. 5 shows a schematic cross section through a system carrier 5 of a first embodiment of the invention.
  • the system carrier 5 has a base substrate 11, on which external contact elements 6 are arranged, which show a rivet-shaped cross section 7.
  • the rivet-shaped cross section consists of a rivet base area 10, a rivet shank area 9 and a rivet head area 8.
  • the structured, electrically insulating layer 18 shown in FIG. 4 is removed in FIG ⁇ -5 H 1 ⁇ ! fr rt t P CQ ö 0 ⁇ P ⁇ ⁇ CQ 3 tr LQ rt P. l C ⁇ ⁇ C ⁇ ⁇ «O fd * - P P- ⁇ i
  • P for P- P 0 O P P 1 Hl C ⁇ CO h CQ ri ⁇ rt ⁇ ⁇ in ⁇ tr ⁇ i tr H ⁇ tr P
  • N 1 ⁇ P P H CQ CO 1 0 ⁇ P- 1 ⁇ rt 3 H, 1 P P p. PJ tr
  • ⁇ i ⁇ PJ s C ⁇ P- ⁇ ti 00 £ - PP ID ⁇ P ⁇ * »PP tr 0: ⁇ P rt ii ⁇ i -> C ⁇ ⁇ rt P Pi: rt C ⁇ Pi P- PN ⁇ J tr ⁇ ⁇ in O in rt Hi 0 J ⁇ r ⁇
  • P P tr tr PJ P Ti N LQ P "rt P P N P ⁇ ⁇ CQ Hi 3 ⁇ J P- s- ⁇ P P fr- CQ>
  • ⁇ rt C ⁇ ⁇ PJ IQ ⁇ H, > ⁇ P P- ⁇ O rt CQ C ⁇ O ⁇ PJ C ⁇ ⁇ ⁇ - rt tr LQ
  • Hi P - P *> Hl ⁇ P- rt • fl CQ ⁇ ⁇ LQ rt ⁇ ⁇ rt LQ P ⁇ 0 rt P C ⁇ tr ti
  • the external contact elements 6 are equipped with a circular plan and the saw marks in the plastic plate run completely in plastic, so that the external contact elements 6 only with their rivet foot area 10, that of plastic on the underside 32 of the component 2 is kept free, can be contacted from the outside.
  • FIG. 10 shows a schematic cross section through a system carrier 5 with an applied semiconductor chip 1 according to a third embodiment of the invention.
  • the semiconductor chip 1 is applied directly to the base substrate 11 with its passive side 33.
  • external contact elements 6 are arranged on the base substrate 11 around the semiconductor chip 1, and the rivet head regions 8 are connected to the contact surfaces 22 of the active side 31 of the semiconductor chip 1 via bond wires 27.
  • Such a system carrier 5 is connected with the aid of the housing-forming plastic mass 4 to form a plastic plate with an attached base substrate 11.
  • the base substrate 11, if it consists of a metal foil, is etched away and then the plastic plate is applied to an adhesive foil and then separated into individual components.
  • FIG. 11 shows a schematic cross section through an electronic component according to a third embodiment of the invention.
  • This component is characterized by its extreme flatness, since even the base height h, as shown in FIG. 8, is additionally saved.
  • a disadvantage of this component is that the passive side 33 of the semiconductor chip 1 simultaneously forms the underside 32 of the electronic component. The underside 33 of the semiconductor chip 1 is thus exposed to environmental influences.
  • Treasure 6 are securely anchored in the plastic mass 4 of the housing 3 due to their rivet-shaped cross-section and have a circular plan in their rivet base region 10. on, which provides a circular contact spot as the external contact surface 23.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Mounting Components In General For Electric Apparatus (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
EP01949240A 2000-06-27 2001-06-07 Systemträger für halbleiterchips und elektronische bauteile sowie herstellungsverfahren für einen systemträger und für elektronische bauteile Withdrawn EP1295336A2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10031204A DE10031204A1 (de) 2000-06-27 2000-06-27 Systemträger für Halbleiterchips und elektronische Bauteile sowie Herstellungsverfahren für einen Systemträger und für elektronische Bauteile
DE10031204 2000-06-27
PCT/DE2001/002097 WO2002001634A2 (de) 2000-06-27 2001-06-07 Systemträger für halbleiterchips und elektronische bauteile sowie herstellungsverfahren für einen systemträger und für elektronische bauteile

Publications (1)

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EP1295336A2 true EP1295336A2 (de) 2003-03-26

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US (2) US6969905B2 (ja)
EP (1) EP1295336A2 (ja)
JP (1) JP2004502303A (ja)
KR (1) KR100614722B1 (ja)
DE (1) DE10031204A1 (ja)
WO (1) WO2002001634A2 (ja)

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Also Published As

Publication number Publication date
US20030102538A1 (en) 2003-06-05
KR20030011932A (ko) 2003-02-11
WO2002001634A3 (de) 2002-06-20
KR100614722B1 (ko) 2006-08-21
US6969905B2 (en) 2005-11-29
US20060060981A1 (en) 2006-03-23
WO2002001634A2 (de) 2002-01-03
DE10031204A1 (de) 2002-01-17
JP2004502303A (ja) 2004-01-22

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