EP0940856A1 - Ferroelektrisches speicherelement und verfahren zur herstellung - Google Patents

Ferroelektrisches speicherelement und verfahren zur herstellung Download PDF

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EP0940856A1
EP0940856A1 EP98919659A EP98919659A EP0940856A1 EP 0940856 A1 EP0940856 A1 EP 0940856A1 EP 98919659 A EP98919659 A EP 98919659A EP 98919659 A EP98919659 A EP 98919659A EP 0940856 A1 EP0940856 A1 EP 0940856A1
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Prior art keywords
ferroelectric
memory device
layer
ferroelectric memory
accordance
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EP98919659A
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French (fr)
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EP0940856A4 (de
EP0940856B1 (de
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Takashi Nakamura
Yoshikazu Fujimori
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties

Definitions

  • the present invention relates to a ferroelectric memory device, more specifically, to ferroelectric materials used for a ferroelectric memory device.
  • FETs Field effect transistors (FETs) using a ferroelectric layer is proposed as a nonvolatile memory device.
  • the FET 12 shown in Fig. 13 is a kind of FET having a structure so called MFMIS (Metal Ferroelectric Metal Insulator Silicon).
  • the FET 12 is formed by means of disposing a gate oxidation layer 4, a floating gate 6, a ferroelectric layer 8, and a control gate 10 in that order on a channel region CH formed in a semiconductor substrate 2.
  • the polarization of the ferroelectric layer 8 is turned over when a positive voltage +V is applied to the control gate 10 while grounding the substrate 2 of the FET 12 (an N channel substrate). Negative electric charges are established in the channel region CH as a result of a remanence polarization remained in the ferroelectric layer 8 even when the positive voltage +V no long be applied to the control gate 10. A condition that the negative electric charges are in the channel region CH corresponds to data "1".
  • a readout voltage Vr is applied to the control gate 10.
  • the readout voltage Vr is set at a value between the threshold voltage Vth1 of the FET 12 which is defined when the data "1" is stored and the threshold voltage Vth0 of the FET 12 which is defined when the data "0" is stored.
  • Judgement of the stored data either in “1” or “0” can be carried out by detecting whether a drain current predetermined flows or not when the readout voltage Vr is applied to the control gate 10. The stored data never be erased after read out the data.
  • nondestructive readout can be carried out using the FET including a ferroelectric layer. Further, such device is capable of composing one memory cell.
  • the FET 12 is considered in a condition that a capacitor Cf (capacity Cf) which includes the ferroelectric layer 8 and a capacitor Cox (capacity Cox) having the gate oxidation layer 4 is connected in series during the writing (see Fig. 2).
  • the divided voltage Vf need to be a large value.
  • the capacitance of the capacitor Cf should be a small value relative to that of the capacitor Cox as it is clear from the equation shown in above.
  • the relative dielectric constant (200 to 1,000) of the PZT composing the ferroelectric layer 8 is much higher than the relative dielectric constant (3.9) of the Sio 2 which composes the gate oxidation layer 4.
  • the melting point of PZT is at a low temperature (800 to 900°C) because PZT contains Pb. This leads lattice defects in an FET requiring heat treatment after forming a ferroelectric layer. Similar problem to PZT may be observed in a ferroelectric material using bismuth (Bi).
  • a ferroelectric memory device includes a ferroelectric layer in which information being stored using its hysteresis characteristics, wherein the ferroelectric layer is composed of a mixed crystal defined by expressions of;
  • the method comprises the steps of:
  • FIG. 1 A view showing a construction of an FET 20 having an MFMIS structure which forms a ferroelectric memory device in an embodiment of the present invention is depicted in Fig. 1.
  • the FET 20 comprises a source region S and a drain region D, both formed in a semiconductor substrate 22 made of silicon.
  • a channel region CH is formed between the source region S and the drain region D.
  • a gate oxidation layer 24 acts as an insulation layer is formed on the channel region CH.
  • the gate oxidation layer 24 is made of SiO 2 .
  • a floating gate 26 forming a lower conductive layer is formed on the gate oxidation layer 24.
  • the floating gate 26 has a stacked structure of Pt/IrO 2 .
  • a control gate 30 acts as an upper conductive layer is formed on the ferroelectric layer 28.
  • the control gate 30 is made of Pt.
  • an equivalent circuit of the FET 20 during the writing is diagrammed in Fig. 2.
  • the equivalent circuit of the FET 20 during the writing is in a formation of connecting a capacitor Cf (capacity Cf) which includes the ferroelectric layer 28 and a capacitor Cox (capacity Cox) having the gate oxidation layer 24 in series.
  • Fig. 3 is a graph showing a relationship between thicknesses tf of a ferroelectric layer 28 and electric fields Ef applied to the capacitor Cf when the thickness tox of the gate oxidation layer 24 is fixed to 10nm as well as using voltages V applied at a point located between the substrate 22 and the control gate 30 as a parameter.
  • Solid curves show the relationship when the relative dielectric constant ⁇ f of the ferroelectric substance is 10
  • dashed curves illustrate the relationship when the relative dielectric constant ⁇ f of the ferroelectric substance is 100.
  • the expression (3) may be formulized in another expression shown in below, V/ ⁇ >Ec ⁇ f/ ⁇ ox ⁇ tox+tf ⁇ k1
  • Fig. 4A is a graph being drawn according to plots showing a relationship between k1 used in the expression (4) and k2 used in the expression (7) of major ferroelectric substances.
  • some of the values used in these expressions are defined as the followings,
  • Both the expressions (8) and (9) need to be satisfied in order to cause the polarization reversal of the ferroelectric layer 28 as well as preventing the dielectric breakdown of the gate oxidation layer 24.
  • Fig. 4A is an enlarged view illustrating the vicinity of the area (z).
  • the ferroelectric layer 28 should be composed of a ferroelectric substance having a high melting point which withstands heat treatments carried out in the vicinity of 800°C.
  • Sr 2 Nb 2 O 7 is selected as a ferroelectric substance which qualities the requirements described in above.
  • a thin film made of Sr 2 Nb 2 O 7 is formed using the Sol-Gel method described later.
  • Fig. 5 is a graph showing x-ray diffraction patterns of a memory device being fabricated using annealing temperatures for crystallization as a parameter. As clearly be recognized from Fig. 5, the peaks show unique characteristics of Sr 2 Nb 2 O 7 appeared on the graph when the annealing temperature is equal to or more 900°C, so that, it is understood that Sr 2 Nb 2 O 7 is in crystallization.
  • Relative dielectric constant ⁇ f of the thin film made of Sr 2 Nb 2 O 7 thus obtained is measured as the vicinity of 45. It is, however, not possible to confirm ferroelectricity (hysteresis characteristics between the voltage applied thereto and the polarization therein) of the film.
  • a curie temperature Tc of the thin film is considered as one of the reasons. Curie temperature is a temperature located at the boundary between temperatures in which a substance indicates ferroelectricity and temperatures in which the substance shows dielectricity. In this connection, the substance indicates ferroelectricity when the temperature of the substance is lower than its curie temperature. It is expected that the thin film made of Sr 2 Nb 2 O 7 shows ferroelectricity in the room temperature according to a principle of crystallographical because the curie temperature Tc of Sr 2 Nb 2 O 7 is at 1342°C.
  • Crystallographical and electric characteristics of Sr 2 Nb 2 O 7 and Sr 2 Ta 2 O 7 are listed on a table shown in Fig. 6.
  • the crystal structure of Sr 2 Nb 2 O 7 and Sr 2 Ta 2 O 7 (both of which have pyramid quadratic structure) is similar to each other.
  • the inventors make a thin film using a mixed crystal made of Sr 2 Nb 2 O 7 and Sr 2 Ta 2 O 7 which satisfies the following condition in experimental basis, that is expressed as the following, Sr 2 (Ta 1-x Nb x ) 2 O 7 wherein 0 ⁇ x ⁇ 1.
  • the mixed crystal consist of Sr 2 (Ta 1-x Nb x ) 2 O 7 changes its crystallographical and electric characteristics consecutively correspond to its mixture ratio.
  • Fig. 7 is a graph showing a relationship between mixture ratios x of Nb in a mixed crystal Sr 2 (Ta 1-x Nb x ) 2 0 7 and a curie temperature of the mixed crystal. It is understood that the mixture ratio x of Nb in the mixed crystal should be xl in order to obtain a curie temperature of Tcl according to the graph.
  • mixed-metal alkoxide composed of Sr, Ta, and Nb, which is dissolved in a solvent is prepared, and the alkoxide thus dissolved is coated on a base substance (this substance becoming the floating gate 26 as a result of patterning, see Fig. 1) having a stacked structure of Pt/IrO 2 .
  • 2-metoxyethernol is used for the solvent.
  • the alkoxide is coated by spin coating method.
  • the solvent is evaporated at a temperature of 180°C.
  • Amorphous layer having a predetermined thickness is formed by carrying out these processes repeatedly.
  • the processes described above are carried out for a total of four times (four coatings). It is not necessary to repeat the processes as described above, the processes may be carried out just once when the predetermined thickness is much thinner than that of above.
  • annealing for crystallization is carried out to the amorphous layer thus formed.
  • the annealing in this embodiment is carried out by rapid thermal annealing (RTA) method. That is, heat treatment using O 2 within a range of 850 to 1000°C is carried out for 1 minutes.
  • RTA rapid thermal annealing
  • the method for forming the thin film made of the mixed crystal composed of Sr 2 (Ta 1-x Nb x ) 2 O 7 is not limited to Sol-Gel method.
  • Other available methods conventionally used such as spattering method, MOCVD method, MOD method, IBS method, PLD method, and the like can be used for forming the thin film.
  • Another layer made of Pt (this layer becoming the control gate 30 as a result of patterning, see Fig. 1) is disposed on the thin film thus obtained by carrying out spattering method.
  • Fig. 8 is a graph showing the x-ray diffraction patterns of the memory device having a ratio x of 0.3 using the annealing temperatures for crystallization as a parameter.
  • the peaks show unique characteristics of Sr 2 (Ta 1-x Nb x ) 2 O 7 appeared on the graph when the annealing temperature is equal to or more 950°C, so that, it is understood that Sr 2 (Ta 1-x Nb x ) 2 O 7 is in crystallization.
  • the surface of the thin film made of Sr 2 (Ta 1-x Nb x ) 2 O 7 was very smooth and fine structure in crystallization.
  • Fig. 9 is a graph showing a relationship between voltages applied to the thin film made of Sr 2 (Ta 1-x Nb x ) 2 O 7 and polarization states generated therein using the value x as a parameter.
  • the relationship between the voltages and the polarization states is measured with a Sawyer tower circuit using a frequency of 1KHz.
  • the axis of abscissas shows the voltages, and the axis of ordinates represents the polarization states.
  • the relationship between the voltages and the polarization states shows hysteresis characteristics when the values of x is in a range of 0.1 ⁇ x ⁇ 0.3. According to Fig.
  • curie temperature Tc of the thin film is in a range of 180°C to 600°C when the values of x are in a range of 0.1 ⁇ x ⁇ 0.3 (As in Fig. 7, curie temperatures Tc of the thin film are either in the vicinity of 410°C or 520°C when the values of x are in 0.2 and 0.3 respectively).
  • remanent polarization Pr is in the largest value such as 0.5 ⁇ c/cm 2 when the values of x is in 0.3. At that time, coercive field Ec was measured at 44KV/cm.
  • Fig. 10 is a graph showing a relationship between bias voltages applied to the thin film of Sr 2 (Ta 1-x Nb x ) 2 0 7 and capacitances thereof using the value x as a parameter.
  • the relationship between the voltages and the capacitances is measured with an LCR meter generating 25mV and 100 KHz (model No. HP4284A).
  • the axis of abscissas shows the bias voltages, and the axis of ordinates represents the capacitances. Sweep rate of the measurement was 0.5V/second. It is clearly understood that the thin film being formed shows hysteresis characteristics when the values of x is in a range of 0.1 ⁇ x ⁇ 0.3.
  • Relative dielectric constant ⁇ r of the thin film was 53 when the value x is 0.3, the dielectric constant being calculated from the capacitance when 0V is applied thereto as the bias voltage.
  • Fig. 11 is a graph showing leakage currents of the thin film made of Sr 2 (Ta 1-x Nb x ) 2 0 7 using the value x as a parameter.
  • the axis of abscissas shows the voltages, and the axis of ordinates represents density of the leakage currents.
  • the density of the leakage currents is the highest value when the value x is 0.3, and it becomes the lowest value when the value x is 0.1.
  • the results might be caused by measurement error.
  • these leakage current density is a relatively small value such as equal or less than 6X10 -7 A/cm 2 when a voltage 3V (in electric field equivalent of approximately 200KV/cm) is applied to the thin film.
  • Sr 2 (Ta 1-x Nb x ) 2 0 7 is used as an example of the mixed crystal which can express as (A1 y1 A2 y2 ... An yn ) 2 (B1 x1 B2 x2 ... Bm xm ) 2 O 7 in the embodiments described above
  • the substance used for forming the thin film to realize the present invention is not limited to Sr 2 (Ta 1-x Nb x ) 2 0 7 .
  • elements belong to IIa group, IIIa group, and lanthanum series may be used as A1, A2, ... An of the mixed crystal expressed as (A1 y1 A2 y2 ... An yn ) 2 (B1 x1 B2 x2 ... Bm xm ) 2 O 7 .
  • the elements belong to IIa group Mg, Ca, Ba and the like may be used in addition to Sr.
  • the elements belong to IIIa group Sc, Y, La, Ac and the like can be used.
  • the elements belong to lanthanum series Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, La and the like may be used.
  • Nb and Ta for example Ti, Zr, Hf, Y and the like may also be used as B1,B2 ... Bm of the mixed crystal expressed as (A1 y1 A2 y2 ... An yn ) 2 (B1 x1 B2 x2 ... Bm xm ) 2 O 7 .
  • the thin film can also be formed using mixed crystals composed any of Ca 2 Nb 2 O 7 , La 2 Ti 2 O 7 , Ce 2 Ti 2 O 7 , Pr 2 Ti 2 O 7 , Nd 2 Ti 2 O 7 , Sm 2 Ti 2 O 7 , Gd 2 Ti 2 O 7 , Y 2 Ti 2 O 7 and the like in addition to Sr 2 Nb 2 O 7 and Sr 2 Ta 2 O 7 .
  • the thin film made of mixed crystal is designed so that curie temperature Tc of which is in a range of 180°C ⁇ x ⁇ 600°C in the embodiments described above, curie temperature of the thin film used in the present invention is not limited to the temperature range.
  • a ferroelectric thin film having desired curie temperature Tc corresponding to the temperature at which the device being in operation is preferred.
  • the ferroelectric thin film according to the present invention is applied to the FET 20 having the MFMIS structure in the embodiments described above, the application of the present invention is not limited to the FET having the structure.
  • the present invention may also be applicable to FETs having other structures, such as any of the FET 40 having MFIS structure shown in Fig. 12A, the FET 50 having the MIFIS structure shown in Fig. 12B, and the FET 60 having the MFS structure shown in Fig. 12C.
  • the FET 40 having the MFIS structure is considered as an equivalent circuit in which a capacitor including an insulation layer 42, another capacitor which comprises a ferroelectric layer 44 is connected in series during the writing.
  • the FET 50 having the MIFIS structure may also be considered as an equivalent circuit having a formation of connecting a capacitor which includes an insulation layer 52, another capacitor which comprises a ferroelectric layer 54, and still another capacitor which includes an insulation layer 56 in series during the writing.
  • the FET 60 having the MFS structure further be considered as an equivalent circuit in which a capacitor including an insulation layer 62 and another capacitor which comprises a ferroelectric layer 64 is connected in series during the writing.
  • the insulation layer 62 made of SiO 2 is formed unintentionally during a process of depositing the ferroelectric layer 64 on a semiconductor substrate 61 of silicon.
  • the application of the present invention is not limited to FETs including a ferroelectric layer.
  • the present invention may also be applicable to other types of memory devices including a first capacitor having a ferroelectric layer and a second capacitor substantially connected to the first capacitor in series.
  • the present invention is applicable generally to memory devices including a ferroelectric material.
  • a ferroelectric memory device in accordance with the present invention is characterized in that, a ferroelectric memory device includes a ferroelectric layer in which information being stored using its hysteresis characteristics, and the ferroelectric layer is composed of a mixed crystal defined by expressions of;
  • dielectric constant of the ferroelectric layer can be reduced by composing the ferroelectric layer with an A 2 B 2 O 7 type crystal.
  • the melting point of the ferroelectric layer may be increased.
  • characteristic values of the ferroelectric layer such as curie temperature related with ferroelectricity thereof can be controlled as desired by composing the layer with a mixed crystal. In this way, a ferroelectric layer having characteristics of desired ferroelectricity, a low dielectric constant, and a high melting point may be obtained.
  • the ferroelectric memory device in accordance with the present invention is characterized in that, curie temperature Tc of the ferroelectric layer is in a range of about 180°C to about 600°C. In this way, a ferroelectric layer which shows stable ferroelectricity within an operating range of -50°C to +150°C can be obtained.
  • the ferroelectric memory device in accordance with the present invention is characterized in that, curie temperature Tc of the ferroelectric layer is in a range of about 500°C to about 600°C. In this way, a ferroelectric layer which shows much stable ferroelectricity can be obtained.
  • the ferroelectric memory device in accordance with the present invention is characterized in that, the ferroelectric memory device includes a first capacitor having the ferroelectric layer, and a second capacitor connected to the first capacitor substantially in series, and information is stored in accordance with a divided voltage applied to the ferroelectric layer of the first capacitor by applying a voltage which corresponds to the information to be stored to both ends of the first capacitor and the second capacitor connected in series.
  • the information is stored in accordance with the divided voltage applied to the ferroelectric layer of the first capacitor by applying a voltage corresponds to the information to be stored to both ends of the first capacitor and the second capacitor connected in series.
  • the divided voltage applied to the first capacitor can be increased using a ferroelectric layer having a low dielectric constant.
  • polarization reversal of the ferroelectric layer can be caused easily during the writing.
  • storing information into the ferroelectric memory device can be carried out easily.
  • the ferroelectric memory device in accordance with the present invention is characterized in that, the ferroelectric memory device comprises, a source region, a drain region, a channel region formed between the source region and the drain region, a substantially insulation layer disposed on the channel region, a ferroelectric layer disposed above the substantially insulation layer, and an upper conductive layer disposed on the ferroelectric layer.
  • the probability of lattice defects in a ferroelectric layer once formed is decreased in an FET requiring heat treatment after forming the ferroelectric layer by using the ferroelectric layer having a high melting point. In this way, it is possible to obtain a ferroelectric memory device with high reliability.
  • the ferroelectric memory device in accordance with the present invention is characterized in that, the ferroelectric memory device has a lower conductive layer between the substantially insulation layer and the ferroelectric layer. In this way, it is possible to obtain a ferroelectric memory device with much high reliability by fabricating it with a structure so called MFMIS (Metal Ferroelectric Metal Insulator Silicon).
  • MFMIS Metal Ferroelectric Metal Insulator Silicon
  • the ferroelectric memory device in accordance with the present invention is characterized in that, the ferroelectric layer is composed of a mixed crystal defined by expressions of;
  • a ferroelectric layer which shows ferroelectricity at a desired temperature range can be formed easily using a mixed crystal composed of Sr 2 Nb 2 O 7 indicating a high curie temperature Tc and Sr 2 Ta 2 O 7 having a low curie temperature Tc.
  • the ferroelectric memory device in accordance with the present invention is characterized in that, the value of x is in a range of about 0.1 to about 0.3. It is, therefore, possible to form a ferroelectric layer which shows ferroelectricity at the room temperature by controlling a mixture ratio of the mixed crystal within the range.
  • the ferroelectric memory device in accordance with the present invention is characterized in that, the value of x is about 0.3. It is, therefore, possible to form a ferroelectric layer which shows much higher ferroelectricity at the room temperature by controlling a mixture ratio of the mixed crystal to the value.
  • the method of manufacturing a ferroelectric memory device in accordance with the present invention is characterized in that, the method comprises the steps of:

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EP98919659A 1997-05-23 1998-05-18 Ferroelektrisches speicherelement und verfahren zur herstellung Expired - Lifetime EP0940856B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP13396597A JP3190011B2 (ja) 1997-05-23 1997-05-23 強誘電体記憶素子およびその製造方法
JP13396597 1997-05-23
PCT/JP1998/002207 WO1998053506A1 (en) 1997-05-23 1998-05-18 Ferroelectric memory element and method of producing the same

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EP0940856A1 true EP0940856A1 (de) 1999-09-08
EP0940856A4 EP0940856A4 (de) 2002-03-27
EP0940856B1 EP0940856B1 (de) 2008-06-11

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US (1) US6097058A (de)
EP (1) EP0940856B1 (de)
JP (1) JP3190011B2 (de)
KR (1) KR100476867B1 (de)
DE (1) DE69839600D1 (de)
WO (1) WO1998053506A1 (de)

Cited By (5)

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WO2001024265A1 (fr) 1999-09-30 2001-04-05 Rohm, Co., Ltd. Memoire non volatile
EP1143525A2 (de) * 2000-03-16 2001-10-10 Yasuo Tarui Ferroelektrisches nichtschwebendes Speicherelement vom Transistortyp
WO2004070736A1 (ja) * 2003-02-05 2004-08-19 Tokyo Electron Limited 強誘電体膜，半導体装置，強誘電体膜の製造方法及び強誘電体膜の製造装置
DE102005051573A1 (de) * 2005-06-17 2006-12-28 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik MIM/MIS-Struktur mit Praseodymtitanat oder Praseodymoxid als Isolatormaterial
US7195928B2 (en) * 2001-08-14 2007-03-27 Rohm Co., Ltd. Method of manufacturing ferroelectric substance thin film and ferroelectric memory using the ferroelectric substance thin film

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US6368919B2 (en) 1999-01-19 2002-04-09 Micron Technology, Inc. Method and composite for decreasing charge leakage
US6495878B1 (en) 1999-08-02 2002-12-17 Symetrix Corporation Interlayer oxide containing thin films for high dielectric constant application
CN1358326A (zh) * 1999-06-10 2002-07-10 塞姆特里克斯公司 高介电常数的金属氧化物薄膜
KR100333669B1 (ko) 1999-06-28 2002-04-24 박종섭 레드니오비움지르코니움타이타니트 용액 형성 방법 및 그를 이용한 강유전체 캐패시터 제조 방법
DE19946437A1 (de) * 1999-09-28 2001-04-12 Infineon Technologies Ag Ferroelektrischer Transistor
JP2002016232A (ja) * 2000-06-27 2002-01-18 Matsushita Electric Ind Co Ltd 半導体記憶装置及びその駆動方法
KR100363393B1 (ko) * 2000-06-28 2002-11-30 한국과학기술연구원 비파괴판독형 불휘발성 기억소자의 메모리 셀 소자 및 그제조 방법
ATE394518T1 (de) * 2001-04-03 2008-05-15 Forschungszentrum Juelich Gmbh Wärmedämmschicht auf basis von la2 zr2 o7 für hohe temperaturen
DE10214159B4 (de) * 2002-03-28 2008-03-20 Qimonda Ag Verfahren zur Herstellung einer Referenzschicht für MRAM-Speicherzellen
NO326130B1 (no) * 2002-10-08 2008-10-06 Enok Tjotta Fremgangsmate for seleksjon og testing av forbindelser som inhiberer eller stimulerer klonal cellevekst
US6912150B2 (en) * 2003-05-13 2005-06-28 Lionel Portman Reference current generator, and method of programming, adjusting and/or operating same
EP1634323A4 (de) * 2003-06-13 2008-06-04 Univ North Carolina State Komplexe oxide zur verwendung in halbleiterbauelementen und diesbezügliche verfahren
KR100655780B1 (ko) * 2004-12-20 2006-12-08 삼성전자주식회사 플래시 메모리 장치 및 그 제조 방법
WO2008126961A1 (en) * 2007-04-12 2008-10-23 University Of Seoul Foundation Of Industry-Academic Cooperation Mfmis-fet, mfmis-ferroelectric memory device, and methods of manufacturing the same
JP2009266967A (ja) * 2008-04-23 2009-11-12 Tohoku Univ 強誘電体膜、強誘電体膜を有する半導体装置、及びそれらの製造方法
JP2010062221A (ja) * 2008-09-01 2010-03-18 Sharp Corp 強誘電体ゲート電界効果トランジスタ、それを用いたメモリ素子及び強誘電体ゲート電界効果トランジスタの製造方法
EP2484794A1 (de) * 2011-02-07 2012-08-08 Siemens Aktiengesellschaft Material mit Pyrochlorstruktur mit Tantal, Verwendung des Materials, Schichtsystem und Verfahren zur Herstellung eines Schichtsystems

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WO2001024265A1 (fr) 1999-09-30 2001-04-05 Rohm, Co., Ltd. Memoire non volatile
US6674109B1 (en) 1999-09-30 2004-01-06 Rohm Co., Ltd. Nonvolatile memory
EP1143525A2 (de) * 2000-03-16 2001-10-10 Yasuo Tarui Ferroelektrisches nichtschwebendes Speicherelement vom Transistortyp
EP1143525A3 (de) * 2000-03-16 2003-11-19 Yasuo Tarui Ferroelektrisches nichtschwebendes Speicherelement vom Transistortyp
US6885048B2 (en) 2000-03-16 2005-04-26 Yasuo Tarui Transistor-type ferroelectric nonvolatile memory element
US7195928B2 (en) * 2001-08-14 2007-03-27 Rohm Co., Ltd. Method of manufacturing ferroelectric substance thin film and ferroelectric memory using the ferroelectric substance thin film
WO2004070736A1 (ja) * 2003-02-05 2004-08-19 Tokyo Electron Limited 強誘電体膜，半導体装置，強誘電体膜の製造方法及び強誘電体膜の製造装置
KR100732930B1 (ko) * 2003-02-05 2007-06-29 동경 엘렉트론 주식회사 강유전체막, 반도체 장치, 강유전체막의 제조 방법 및강유전체막의 제조 장치
CN101215684B (zh) * 2003-02-05 2010-09-01 大见忠弘 铁电膜、半导体装置、铁电膜的制造方法及其制造装置
DE102005051573A1 (de) * 2005-06-17 2006-12-28 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik MIM/MIS-Struktur mit Praseodymtitanat oder Praseodymoxid als Isolatormaterial
DE102005051573B4 (de) * 2005-06-17 2007-10-18 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik MIM/MIS-Struktur mit Praseodymtitanat als Isolatormaterial

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KR20000023760A (ko) 2000-04-25
KR100476867B1 (ko) 2005-03-17
JPH10326872A (ja) 1998-12-08
DE69839600D1 (de) 2008-07-24
EP0940856A4 (de) 2002-03-27
JP3190011B2 (ja) 2001-07-16
US6097058A (en) 2000-08-01
WO1998053506A1 (en) 1998-11-26
EP0940856B1 (de) 2008-06-11

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