EP0852064A2 - Verfahren zum erzeugen sehr kleiner strukturweiten auf einem halbleitersubstrat - Google Patents
Verfahren zum erzeugen sehr kleiner strukturweiten auf einem halbleitersubstratInfo
- Publication number
- EP0852064A2 EP0852064A2 EP96938929A EP96938929A EP0852064A2 EP 0852064 A2 EP0852064 A2 EP 0852064A2 EP 96938929 A EP96938929 A EP 96938929A EP 96938929 A EP96938929 A EP 96938929A EP 0852064 A2 EP0852064 A2 EP 0852064A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- oxide
- microstructure
- width
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 17
- 230000015654 memory Effects 0.000 claims abstract description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000007667 floating Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Definitions
- transistors with a minimal gate length are used as drivers and those with a minimal width are used as active load elements.
- the transistor width has a direct effect on the gate capacitance, which forms a capacitive load for the previous stage, and the resistance value for an active load element.
- the minimum transistor width is determined by the minimum active path width when the field isolation is generated by a LOCOS (Local Cocidation of Silicon) process. In a certain generation of lithography, this is usually about one and a half to twice as large as the minimum gate length.
- non-volatile memories such as Flotox-EEPROM or flash memories are also formed with MOS transistors, that is to say with elements with a source, a channel and a drain region.
- MOS transistors that is to say with elements with a source, a channel and a drain region.
- the information is stored in a floating gate above the channel region, which is isolated from it by a gate oxide.
- This charge is changed by programming or erasing by Fowler-Nordheim tunneling of electrons between the floating gate and the semiconductor substrate through a very thin dielectric, which is formed by a very thin window, the tunnel window, in the gate oxide.
- the voltage required for this corresponding to a field strength of over 10 MV / cm, is capacitively coupled in via a control gate.
- the necessary voltage at the control gate to initiate the tunnel process depends on two factors: the efficiency of the coupling of the voltage applied to the control gate, i.e. the coupling factor, which is essentially given by the area ratio of the control gate to the tunnel window, and the Thickness of the tunnel oxide.
- the smallest possible programming voltage requires a small tunnel window with a thin tunnel oxide with the largest possible overlap of the control gate over the floating gate.
- the spacer 8 is then removed. For this it is necessary that it can be selectively etched both with respect to the silicon oxide and with respect to the polysilicon. This condition is met by using silicon nitride for the first layer. But other materials can also be used are used, it is essential that they can be etched selectively against one another.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19534780 | 1995-09-19 | ||
DE19534780A DE19534780A1 (de) | 1995-09-19 | 1995-09-19 | Verfahren zum Erzeugen sehr kleiner Strukturweiten auf einem Halbleitersubstrat |
PCT/DE1996/001697 WO1997011483A2 (de) | 1995-09-19 | 1996-09-10 | Verfahren zum erzeugen sehr kleiner strukturweiten auf einem halbleitersubstrat |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0852064A2 true EP0852064A2 (de) | 1998-07-08 |
Family
ID=7772595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP96938929A Ceased EP0852064A2 (de) | 1995-09-19 | 1996-09-10 | Verfahren zum erzeugen sehr kleiner strukturweiten auf einem halbleitersubstrat |
Country Status (8)
Country | Link |
---|---|
US (1) | US6027972A (ko) |
EP (1) | EP0852064A2 (ko) |
JP (1) | JPH11512568A (ko) |
KR (1) | KR19990044687A (ko) |
CN (1) | CN1202981A (ko) |
DE (1) | DE19534780A1 (ko) |
RU (1) | RU2168797C2 (ko) |
WO (1) | WO1997011483A2 (ko) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19643185C2 (de) * | 1996-10-18 | 1998-09-10 | Siemens Ag | Dual-Gate-Speicherzelle und Verfahren zur Herstellung einer nichtflüchtigen Speicherzelle |
US6150245A (en) * | 1997-02-27 | 2000-11-21 | Nec Corporation | Method of manufacturing a field effect transistor |
JP4081854B2 (ja) * | 1998-05-11 | 2008-04-30 | 沖電気工業株式会社 | 半導体装置の製造方法 |
JP2002100688A (ja) | 2000-09-22 | 2002-04-05 | Oki Electric Ind Co Ltd | 不揮発性半導体メモリの製造方法 |
US6740557B1 (en) | 2001-07-02 | 2004-05-25 | Taiwan Semiconductor Manufacturing Company | Spacer like floating gate formation |
ITMI20022785A1 (it) * | 2002-12-30 | 2004-06-30 | St Microelectronics Srl | Processo per la fabbricazione di celle di memoria |
ITMI20022784A1 (it) * | 2002-12-30 | 2004-06-30 | St Microelectronics Srl | Processo per la fabbricazione di celle di memoria |
US20050239250A1 (en) * | 2003-08-11 | 2005-10-27 | Bohumil Lojek | Ultra dense non-volatile memory array |
JP2005183763A (ja) * | 2003-12-22 | 2005-07-07 | Toshiba Microelectronics Corp | 不揮発性メモリを含む半導体装置の製造方法 |
DE102006037045B4 (de) * | 2006-08-08 | 2011-05-05 | Infineon Technologies Austria Ag | Herstellungsverfahren zum Erzeugen einer Halbleitervorrichtung |
CN107437548B (zh) * | 2016-05-26 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法、电子装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4513397A (en) * | 1982-12-10 | 1985-04-23 | Rca Corporation | Electrically alterable, nonvolatile floating gate memory device |
US4558339A (en) * | 1982-03-09 | 1985-12-10 | Rca Corporation | Electrically alterable, nonvolatile floating gate memory device |
JPS61222175A (ja) * | 1985-03-01 | 1986-10-02 | Fujitsu Ltd | 半導体記憶装置の製造方法 |
JP2547622B2 (ja) * | 1988-08-26 | 1996-10-23 | 三菱電機株式会社 | 不揮発性半導体記憶装置 |
JPH05190809A (ja) * | 1992-01-14 | 1993-07-30 | Kawasaki Steel Corp | 半導体装置の製造方法 |
US5236853A (en) * | 1992-02-21 | 1993-08-17 | United Microelectronics Corporation | Self-aligned double density polysilicon lines for ROM and EPROM |
US5225362A (en) * | 1992-06-01 | 1993-07-06 | National Semiconductor Corporation | Method of manufacturing a full feature high density EEPROM cell with poly tunnel spacer |
KR0150048B1 (ko) * | 1994-12-23 | 1998-10-01 | 김주용 | 플래쉬 이이피롬 셀 및 그 제조방법 |
KR0166840B1 (ko) * | 1995-05-12 | 1999-01-15 | 문정환 | 리세스 채널 구조를 갖는 반도체 소자 및 그의 제조방법 |
US5854501A (en) * | 1995-11-20 | 1998-12-29 | Micron Technology, Inc. | Floating gate semiconductor device having a portion formed with a recess |
DE69630864T2 (de) * | 1996-01-31 | 2004-11-04 | Sgs-Thomson Microelectronics S.R.L., Agrate Brianza | Verfahren zur Herstellung nichtflüchtiger Speicheranordnungen mit Tunneloxid |
US5750428A (en) * | 1996-09-27 | 1998-05-12 | United Microelectronics Corp. | Self-aligned non-volatile process with differentially grown gate oxide thickness |
US5786614A (en) * | 1997-04-08 | 1998-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Separated floating gate for EEPROM application |
-
1995
- 1995-09-19 DE DE19534780A patent/DE19534780A1/de not_active Withdrawn
-
1996
- 1996-09-10 CN CN96198424A patent/CN1202981A/zh active Pending
- 1996-09-10 EP EP96938929A patent/EP0852064A2/de not_active Ceased
- 1996-09-10 KR KR1019980701943A patent/KR19990044687A/ko not_active Application Discontinuation
- 1996-09-10 RU RU98107250/28A patent/RU2168797C2/ru active
- 1996-09-10 JP JP9512303A patent/JPH11512568A/ja not_active Ceased
- 1996-09-10 WO PCT/DE1996/001697 patent/WO1997011483A2/de not_active Application Discontinuation
-
1998
- 1998-03-19 US US09/044,533 patent/US6027972A/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
---|
See references of WO9711483A2 * |
Also Published As
Publication number | Publication date |
---|---|
KR19990044687A (ko) | 1999-06-25 |
CN1202981A (zh) | 1998-12-23 |
WO1997011483A2 (de) | 1997-03-27 |
US6027972A (en) | 2000-02-22 |
DE19534780A1 (de) | 1997-03-20 |
WO1997011483A3 (de) | 1997-06-12 |
JPH11512568A (ja) | 1999-10-26 |
RU2168797C2 (ru) | 2001-06-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3816358C2 (ko) | ||
DE19617632C2 (de) | Verfahren zur Herstellung einer nichtflüchtigen Speicherzelle | |
DE69527388T2 (de) | EEPROM-Zelle mit Isolationstransistor und Betriebs- und Herstellungsverfahren | |
DE69130163T2 (de) | Verfahren zur Herstellung einer MOS-EEPROM-Transistorzelle mit schwebendem Gate | |
DE19747776C2 (de) | Flash-Halbleiterspeicher mit Stapelgate und Verfahren zu dessen Herstellung | |
DE19612948B4 (de) | Verfahren zur Herstellung einer Halbleitereinrichtung mit vertiefter Kanalstruktur | |
DE4114344C2 (de) | Herstellungsverfahren und Aufbau einer nicht-flüchtigen Halbleiterspeichereinrichtung mit einer Speicherzellenanordnung und einem peripheren Schaltkreis | |
DE19808182C1 (de) | Elektrisch programmierbare Speicherzellenanordnung und ein Verfahren zu deren Herstellung | |
DE4404270C2 (de) | Halbleiterspeichervorrichtungen, die Information elektrisch schreiben und löschen können und Verfahren zur Herstellung derselben | |
DE69218048T2 (de) | Verfahren zur Herstellung einer nichtflüchtigen Speicherzelle und dadurch hergestellte Speicherzelle | |
DE3033333A1 (de) | Elektrisch programmierbare halbleiterspeichervorrichtung | |
DE2741152A1 (de) | Speicherzelle fuer einen silizium- gate-n-kanal-mos-direktzugriffspeicher und verfahren zu ihrer herstellung | |
DE2716691A1 (de) | Feldeffekttransistor und verfahren zu dessen herstellung | |
DE10228565A1 (de) | Nicht-flüchtige Speichervorrichtung und Herstellungsverfahren derselben | |
DE19951930C2 (de) | Elektrisch löschbare, programmierbare Festwertspeicher mit Abtast- und Auswahl-Transistorgateelektrode und Verfahren zu ihrer Herstellung | |
WO1997011483A2 (de) | Verfahren zum erzeugen sehr kleiner strukturweiten auf einem halbleitersubstrat | |
EP1504471B1 (de) | Schichtanordnung sowie speicheranordnung | |
DE19807010B4 (de) | Verfahren zur Herstellung einer nichtflüchtigen Speichereinrichtung | |
EP2012359B1 (de) | Nichtflüchtige Zweitransistor-Halbleiterspeicherzelle sowie zugehöriges Herstellungsverfahren | |
DE10324550B4 (de) | Herstellungsverfahren für eine NROM-Halbleiterspeichervorrichtung | |
DE68928501T2 (de) | Verfahren und apparat zur herstellung eines seitenwandkontakts in einer elektrisch veränderbaren nichtflüchtigen speicherzelle | |
DE60207658T2 (de) | Nichtflüchtiger Halbleiterspeicher und Verfahren zu dessen Herstellung | |
DE19748495C2 (de) | EEPROM-Zellstruktur und Verfahren zum Programmieren bzw. Löschen ausgewählter EEPROM-Zellstrukturen sowie EEPROM-Zellenfeld | |
DE69326749T2 (de) | Nichtflüchtiger Speicher mit Schutzdiode | |
DE4123158C2 (de) | Verfahren zur Herstellung von zueinander parallel ausgerichteten Leiterschichtabschnitten |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19980304 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT CH DE ES FR GB IT LI |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: INFINEON TECHNOLOGIES AG |
|
GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
17Q | First examination report despatched |
Effective date: 20011015 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED |
|
18R | Application refused |
Effective date: 20020418 |