EP0852064A2

EP0852064A2 - Method of producing very small structural widths on a semiconductor substrate

Info

Publication number: EP0852064A2
Application number: EP96938929A
Authority: EP
Inventors: Martin Kerber
Original assignee: Infineon Technologies AG; Siemens AG
Current assignee: Infineon Technologies AG
Priority date: 1995-09-19
Filing date: 1996-09-10
Publication date: 1998-07-08
Also published as: CN1202981A; KR19990044687A; JPH11512568A; RU2168797C2; WO1997011483A3; US6027972A; WO1997011483A2; DE19534780A1

Abstract

The invention concerns a method of producing a very small structural width on a semiconductor substrate (1; 10) by producing a microstructure (8; 70) as the result of isotropic etching of a first layer (6) deposited over an edge and removing the edge-forming structure (7; 60). The width of the microstructure (8; 70) is approximately the same thickness as the deposited layer. An underlying polysilicon (5, 50) layer is then selectively oxidised. The small structural width can be the cross section through the channel of a flasch memory cell.

Description

description

Method for producing very small structure widths on a semiconductor substrate

In integrated MOS circuits, transistors with a minimal gate length are used as drivers and those with a minimal width are used as active load elements. In the case of load elements, the transistor width has a direct effect on the gate capacitance, which forms a capacitive load for the previous stage, and the resistance value for an active load element. In known manufacturing methods for integrated MOS circuits, the minimum transistor width is determined by the minimum active path width when the field isolation is generated by a LOCOS (Local Cocidation of Silicon) process. In a certain generation of lithography, this is usually about one and a half to twice as large as the minimum gate length.

However, a smaller transistor width is desired, since this has a positive effect on the transistor area, gate area and thus gate oxide yield and the input capacitance of active load elements.

The cells of non-volatile memories such as Flotox-EEPROM or flash memories are also formed with MOS transistors, that is to say with elements with a source, a channel and a drain region. In the case of such memory cells, the information is stored in a floating gate above the channel region, which is isolated from it by a gate oxide. This charge is changed by programming or erasing by Fowler-Nordheim tunneling of electrons between the floating gate and the semiconductor substrate through a very thin dielectric, which is formed by a very thin window, the tunnel window, in the gate oxide. The voltage required for this, corresponding to a field strength of over 10 MV / cm, is capacitively coupled in via a control gate. The necessary voltage at the control gate to initiate the tunnel process depends on two factors: the efficiency of the coupling of the voltage applied to the control gate, i.e. the coupling factor, which is essentially given by the area ratio of the control gate to the tunnel window, and the Thickness of the tunnel oxide.

The smallest possible programming voltage requires a small tunnel window with a thin tunnel oxide with the largest possible overlap of the control gate over the floating gate.

In the case of flash memory cells, tunneling takes place in an overlap area of the floating gate and the drain area. In the manufacture of the gate oxide by thermal oxidation of the gate areas in the one generated using a LOCOS process

Field oxides occur at the field oxide edges, which lead to inhomogeneous current injection and reduced oxide reliability. These process-related thinning must be prevented by a correspondingly thicker nominal tunnel oxide. In addition, the minimum tunnel oxide thickness is limited by the occurrence of "abnormal gate leakage currents" after Fowler-Nordheim injection in the case of ultra-thin oxides.

This means that in order to reduce the programming voltage, the tunnel window must first of all be reduced in order to achieve a high coupling factor.

This can happen in two directions. Firstly by reducing the overlap area and secondly by reducing the channel width. The field isolation is usually carried out by a LOCOS process, so that the channel width is limited by the structure resolution of the photolithography.

In the case of EEPROM memory cells, tunneling takes place via a tunnel window in the gate oxide above the channel area. Are here too the dimensions of the window are limited by the structure resolution of the photolithography.

From JP 5-190809 A2 it is known to etch trenches isolated from one another by means of a spacer technology in an oxide-polysilicon-oxide-polysilicon layer structure applied to a semiconductor substrate, so that the width of the trenches becomes very small and the remaining structures Display stacked gates with a high areal density. However, the dimension of the gate electrodes is not influenced by the spacer technology.

The publication "IBM Technical Disclosure Bulletin, Vol. 28, No. 6, November 1985" discloses the production of a GaAs FET with a gate electrode of very short length, whereby this

Length is determined by a spacer technology. However, the gate electrode is in direct contact with the channel area, so that a Schottky contact results. In addition, a special layer structure is used to produce the Schottky gate electrode, which is not readily transferable to silicon MOS technology.

The object of the present invention is to specify a method for producing very small feature sizes on a semiconductor substrate, in which the feature sizes are not limited by photolithography.

The object is achieved by a method for producing a very small structure width according to claim 1 and a method for producing a gate electrode with a very small width according to claim 5. Advantageous further developments are specified in the respective subclaims.

According to claim 1, a structure is first applied which has an edge at the point at which the small structure width is to be produced. A first layer is then deposited. This covers the entire surface, so too the edge. This first layer is then anisotropically etched back until the horizontal portions of this layer have been completely removed. A residue remains on the edge, the width of which is approximately equal to the thickness of the deposited layer. This rest is usually referred to as a spacer. The material of the structure is selected so that it can be selectively etched with respect to the material of the first layer. After this etching, only the rest of the first layer, the spacer, remains. This forms an oxidation barrier for the oxidation of the ones below

Layer. This means that only the area outside the spacer is oxidized.

After removal of the spacer, the materials being selected such that the material of the spacer, that is to say the first layer, can be etched selectively with respect to the underlying second layer and the oxide layer previously produced, a small linear structure width corresponding to the dimensions of the spacer remains in the oxide layer. The oxide layer can thus be used as an etching mask for the underlying second layer.

In the case of anisotropic etching, the layer underneath is only etched in depth, so that after removal of the oxide layer it can be used as an etching mask for a layer underneath this.

If successive layers can be etched selectively in the manner according to the invention, the respective upper layer can be used as an etching mask for the layer below, the structure width being retained in the case of anisotropic etching and corresponding approximately to the layer thickness of the first layer, which is easily reproducible and can be chosen smaller than the structure resolution of known lithographies in the optical field. Preferred materials are silicon nitride for the first layer and polysilicon for the second layer. These can be etched well against one another and also against silicon oxide. The structure forming the edge is preferably formed with TEOS (tetraethyl-o.rtho-S.ilan).

The invention can be used both in field insulation using the LOCOS process and with a silicon oxide-polysilicon-silicon oxide sandwich insulation layer. In the first case, a layer must be deposited between the oxide layer and the second layer, which is preferably a polysilicon layer, against which silicon oxide can be selectively etched. Silicon nitride is preferably used here.

The small one that can be produced with the method according to the invention

Structure width can advantageously be used both for generating very narrow gates in MOS transistors to form active load elements and very small tunnel windows in Flotox-EEPROM memory cells and also very small channel widths in flash memory cells.

The invention will be explained in more detail below with the aid of figures using exemplary embodiments. Show:

FIGS. 1A to IH schematically show the sequence according to the invention of a manufacturing process with a small structure width in the case of an oxide-polysilicon-oxide sandwich insulation,

FIGS. 2A to 2F schematically show the sequence according to the invention of a manufacturing process with a small structural width in a field isolation by means of the LOCOS process and

3 shows the cross-section through a flash memory cell with a narrow one according to the invention Channel in an oxide-polysilicon-oxide sandwich insulation layer.

The individual steps of a manufacturing process for producing a small feature size on a semiconductor substrate are shown in FIGS. 1A to IH. The same layers have the same reference symbols.

A thin oxide layer 2 has been produced on a semiconductor substrate 1. A doped polysilicon layer 3 has been deposited thereon, on which an oxide layer 4 has been produced. A polysilicon layer 5 has been deposited again above this oxide-polysilicon-oxide sandwich insulation layer 2, 3, 4. A TEOS layer was deposited on top and structured by means of photolithography, so that a structure 7 with a steep edge was created. A silicon nitride layer 6 was deposited over this structure 7 and the free area of the polysilicon layer 5. This state is shown in FIG. 1A.

The silicon nitride layer 6 is etched back anisotropically, so that only a residue 8 - a so-called spacer - of this silicon nitride layer 6 remains at the edge of the structure 7. The structure 7 is then removed and the underlying polysilicon layer 5 is oxidized. The spacer 8 remaining on the edge of the structure 7 acts as an oxidation barrier, so that the polysilicon layer 5 is oxidized only around it and forms an oxide layer 9 outside the spacer region 8. This state is shown in Figure IB.

The spacer 8 is then removed. For this it is necessary that it can be selectively etched both with respect to the silicon oxide and with respect to the polysilicon. This condition is met by using silicon nitride for the first layer. But other materials can also be used are used, it is essential that they can be etched selectively against one another.

FIG. IC now shows how, in addition to the small structure width, a further structure can be produced in a conventional manner by means of a photomask 10. The photomask 10 serves to etch areas in the silicon oxide layer 9. The photomask 10 is then removed again and the underlying polysilicon 5 is anisotropically etched using the oxide layer 9 serving as an etching mask. This state is shown in FIG. ID.

As shown in FIG. IE, the silicon oxide 9 is then anisotropically etched, which means that the oxide layer 4 is structured at the same time.

The polysilicon layer 5 is then anisotropically etched, as a result of which the polysilicon layer 3 is structured at the same time. This state is shown in Figure IF.

As shown in FIG. IG, the thin oxide layer 2 is now etched, as a result of which the upper oxide layer 4 is also etched. Subsequently, as shown in FIG. IH, the exposed semiconductor substrate 1 is thermally oxidized to a desired oxide thickness. As a result, the previously exposed edges of the polysilicon layer 2 are also covered with an oxide and thus isolated again.

In FIG. IH, a "normal" structure width, as can be produced by a conventional photolithography step, is shown in the right part and a very small structure width, as can be realized by the method according to the invention, in the left part.

This small structure width can be, for example, the cross section through the channel of a flash memory cell. To do this, as shown in FIG. 3, a conductive one Layer 11 are applied as a floating gate, over which a further conductive layer 13 is deposited as a control gate, separated by an insulation layer 12. This small structure width enables a very narrow tunnel area to be created, which enables a favorable coupling factor, which in turn allows a lower programming or erasure voltage. This small channel width also makes the memory cell smaller.

The small structure width can, however, also be used advantageously for "normal" MOS transistors which are used as active load elements, since this enables transistors of very small width to be produced, which has a small gate area and thus a low gate capacitance to have.

FIGS. 2A to 2F show the use of the method according to the invention in field isolation, as is customary, for example, in Flotox-EEPROM memory cells.

In Flotox EEPROM memory cells, the floating gate is separated from the channel area by a thin gate oxide. In order to achieve lower programming and erasing voltages, it is necessary to create a small tunnel window in this gate oxide, the oxide thickness of which should be thinner than the gate oxide. The individual steps for generating this small tunnel window are shown in FIGS. 2A to 2F.

In the illustration in FIG. 2A, a field oxide 20 was structured on a semiconductor substrate 100 by means of a LOCOS process and a gate oxide 30 was generated. A silicon nitride layer 40 was deposited thereon and in turn a polysilicon layer 50. A TEOS layer was deposited on the polysilicon layer 50, which was structured by means of conventional photolithography, so that a structure 60 was formed. A silicon nitride layer was deposited over this structure 60 and the polysilicon layer 50 and then anisotropically etched back so that spacers 70 remain on the edges of the structure 60. This state is shown in Figure 2A.

After the selective removal of the structure 60, the polysilicon layer 50 is oxidized, so that an oxide layer 80 is formed around the spacer 70, which acts as an oxidation barrier, as shown in FIG. 2B. After the spacer 70 has been removed, the oxide layer 80 is used as an etching mask for the underlying polysilicon layer 50. This state is shown in Figure 2C.

Then the oxide layer 80 is removed and the underlying polysilicon layer 50 is used as an etching mask for the silicon nitride layer 40 below it.

The silicon nitride layer 40 is necessary so that the field and gate oxides are not attacked when the oxide layer 80 is removed. FIG. 2D shows the state with the already structured silicon nitride layer 40.

The polysilicon layer 50 is then removed and the gate oxide is etched back to the semiconductor substrate 100 by means of the silicon nitride layer 40 serving as an etching mask. This state is shown in FIG. 2E.

The silicon nitride layer 40 is then removed and a thin tunnel oxide is produced by thermal oxidation in the small structure width 90 produced in the manner according to the invention, which represents the tunnel window. This is shown in Figure 2F.

Since the spacer 70 according to FIG. 2A is produced on the edge of a structure 60, the trench forming the small structure width is always in the form of a closed ring. In the case of a flotox-EEPROM memory cell array, this ring can always define the tunnel window of two mirror-symmetrical memory cells.

If the ring is to be separated, a further photographic technology step is necessary with which the nitride web can be structured immediately before the polysilicon layer 50 is oxidized.

With the proposed process control, tunnel windows can be produced in the form of extremely narrow strips. Their area is up to a factor of 10 smaller than that which can be produced using conventional technology.

Claims

claims

1. A method for producing a very small structure width on a semiconductor substrate (100) by producing a microstructure (70) as a result of anisotropic etching of a first layer deposited over an edge and removing the structure (60) forming the edge, the width the microstructure (70) is approximately equal to the thickness of the deposited first layer and the microstructure (70) is an oxidation barrier in the event of an oxidation of a second layer (50) lying under the microstructure (70), so that that produced around the microstructure (70) After removal of the microstructure (70), oxide (80) serves as an etching mask for the layer (s) underneath, the properties of the materials of the first and second layers and of the oxide being such that they each can be selectively etched, characterized in that on the semiconductor substrate (10) and under the second layer (50) covered by a nitride layer (40) field oxide areas (20) and gate oxide regions (30) are applied and the very small structure width is generated in the region of the gate oxide regions (30).

2. The method according to claim l, characterized in that the first layer (6) with silicon nitride and the second

Layer (5; 50) is formed with polysilicon.

3. The method according to claim 1 or 2, characterized in that the uppermost layer is used as an etching mask for the underlying layer.

4. The method according to any one of claims 1 to 3, characterized ge indicates that the small structure width defines the length of a tunnel window (90) in an EEPROM memory cell.

5. A method for producing a gate electrode with a very small width, with the steps: a) producing a silicon oxide-polysilicon-silicon oxide layer structure (2, 3, 4) on a substrate surface

⁽ 1 ⁾ , b) a first layer (5) is produced on this layer structure, c) a structure (7) is produced on the first layer (5), d) via the first layer (5) and the structure ( 7) a second layer (6) is deposited, which can be selectively etched with respect to the first layer, e) the second layer (6) is etched anisotropically, so that only one microstructure (8) is on the edge of the structure (7 ) remains, f) the structure (7) is removed, g) on the first layer (5) an oxide (9) is produced around the microstructure (8) acting as an oxide barrier, h) the microstructure (8) is removed, i ) the first layer (5) lying under the oxide (9) is etched anisotropically, the oxide layer (9) structured by means of the microstructure (8) acting as an etching mask, j) the oxide layer (9) is removed, k) the one under the The first layer (5) of the upper silicon oxide layer (4) of the layer structure (2, 3, 4) is formed by means of the first layer (5) functioning as an etching mask. anisotropically etched,

1) the first layer (5) is removed, m) the polysilicon layer (3) lying below the upper silicon oxide layer (4) and the lower silicon oxide layer (2) below the layer structure (2, 3, 4) are removed by means of the upper silicon oxide layer (4) functioning as an etching mask is anisotropically etched up to the substrate surface, n) the substrate surface and the wall surfaces of the trench formed are thermally oxidized, o) the trench is filled and covered with a polysilicon layer which acts as a gate electrode (11) and extends into the trench.

6. The method according to claim 5, characterized in that the first layer (5) is formed with polysilicon and the second layer (6) with silicon nitride.

7. The method according to any one of claims 5 or 6, characterized ge indicates that the gate electrode (11) is the control electrode in a MOS transistor.

8. The method according to any one of claims 5 or 6, characterized in that the gate electrode (11) is the floating electrode in a flash EEPROM memory cell.