EP0852064A2 - Procede permettant de creer des largeurs structurales tres reduites sur un substrat a semi-conducteur - Google Patents

Procede permettant de creer des largeurs structurales tres reduites sur un substrat a semi-conducteur

Info

Publication number
EP0852064A2
EP0852064A2 EP96938929A EP96938929A EP0852064A2 EP 0852064 A2 EP0852064 A2 EP 0852064A2 EP 96938929 A EP96938929 A EP 96938929A EP 96938929 A EP96938929 A EP 96938929A EP 0852064 A2 EP0852064 A2 EP 0852064A2
Authority
EP
European Patent Office
Prior art keywords
layer
oxide
microstructure
width
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP96938929A
Other languages
German (de)
English (en)
Inventor
Martin Kerber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, Siemens AG filed Critical Infineon Technologies AG
Publication of EP0852064A2 publication Critical patent/EP0852064A2/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Definitions

  • transistors with a minimal gate length are used as drivers and those with a minimal width are used as active load elements.
  • the transistor width has a direct effect on the gate capacitance, which forms a capacitive load for the previous stage, and the resistance value for an active load element.
  • the minimum transistor width is determined by the minimum active path width when the field isolation is generated by a LOCOS (Local Cocidation of Silicon) process. In a certain generation of lithography, this is usually about one and a half to twice as large as the minimum gate length.
  • non-volatile memories such as Flotox-EEPROM or flash memories are also formed with MOS transistors, that is to say with elements with a source, a channel and a drain region.
  • MOS transistors that is to say with elements with a source, a channel and a drain region.
  • the information is stored in a floating gate above the channel region, which is isolated from it by a gate oxide.
  • This charge is changed by programming or erasing by Fowler-Nordheim tunneling of electrons between the floating gate and the semiconductor substrate through a very thin dielectric, which is formed by a very thin window, the tunnel window, in the gate oxide.
  • the voltage required for this corresponding to a field strength of over 10 MV / cm, is capacitively coupled in via a control gate.
  • the necessary voltage at the control gate to initiate the tunnel process depends on two factors: the efficiency of the coupling of the voltage applied to the control gate, i.e. the coupling factor, which is essentially given by the area ratio of the control gate to the tunnel window, and the Thickness of the tunnel oxide.
  • the smallest possible programming voltage requires a small tunnel window with a thin tunnel oxide with the largest possible overlap of the control gate over the floating gate.
  • the spacer 8 is then removed. For this it is necessary that it can be selectively etched both with respect to the silicon oxide and with respect to the polysilicon. This condition is met by using silicon nitride for the first layer. But other materials can also be used are used, it is essential that they can be etched selectively against one another.

Abstract

L'invention concerne un procédé permettant de créer des largeurs structurales très réduites sur un substrat à semi-conducteur (1; 10), pour donner lieu à une microstructure (8; 70) suite à l'attaque chimique isotrope d'une première couche (6) déposée sur une arête et à l'élimination de la structure (7; 60) formant l'arête, la largeur de la microstructure (8; 70) correspondant approximativement à l'épaisseur de la couche déposée. Une couche de polysilicium (5, 50) située dessous est ensuite oxydée de manière sélective. La largeur structurale réduite peut être la section transversale du canal d'une cellule mémoire flash.
EP96938929A 1995-09-19 1996-09-10 Procede permettant de creer des largeurs structurales tres reduites sur un substrat a semi-conducteur Ceased EP0852064A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19534780A DE19534780A1 (de) 1995-09-19 1995-09-19 Verfahren zum Erzeugen sehr kleiner Strukturweiten auf einem Halbleitersubstrat
DE19534780 1995-09-19
PCT/DE1996/001697 WO1997011483A2 (fr) 1995-09-19 1996-09-10 Procede permettant de creer des largeurs structurales tres reduites sur un substrat a semi-conducteur

Publications (1)

Publication Number Publication Date
EP0852064A2 true EP0852064A2 (fr) 1998-07-08

Family

ID=7772595

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96938929A Ceased EP0852064A2 (fr) 1995-09-19 1996-09-10 Procede permettant de creer des largeurs structurales tres reduites sur un substrat a semi-conducteur

Country Status (8)

Country Link
US (1) US6027972A (fr)
EP (1) EP0852064A2 (fr)
JP (1) JPH11512568A (fr)
KR (1) KR19990044687A (fr)
CN (1) CN1202981A (fr)
DE (1) DE19534780A1 (fr)
RU (1) RU2168797C2 (fr)
WO (1) WO1997011483A2 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19643185C2 (de) * 1996-10-18 1998-09-10 Siemens Ag Dual-Gate-Speicherzelle und Verfahren zur Herstellung einer nichtflüchtigen Speicherzelle
US6150245A (en) * 1997-02-27 2000-11-21 Nec Corporation Method of manufacturing a field effect transistor
JP4081854B2 (ja) * 1998-05-11 2008-04-30 沖電気工業株式会社 半導体装置の製造方法
JP2002100688A (ja) 2000-09-22 2002-04-05 Oki Electric Ind Co Ltd 不揮発性半導体メモリの製造方法
US6740557B1 (en) 2001-07-02 2004-05-25 Taiwan Semiconductor Manufacturing Company Spacer like floating gate formation
ITMI20022784A1 (it) * 2002-12-30 2004-06-30 St Microelectronics Srl Processo per la fabbricazione di celle di memoria
ITMI20022785A1 (it) * 2002-12-30 2004-06-30 St Microelectronics Srl Processo per la fabbricazione di celle di memoria
US20050239250A1 (en) * 2003-08-11 2005-10-27 Bohumil Lojek Ultra dense non-volatile memory array
JP2005183763A (ja) * 2003-12-22 2005-07-07 Toshiba Microelectronics Corp 不揮発性メモリを含む半導体装置の製造方法
DE102006037045B4 (de) * 2006-08-08 2011-05-05 Infineon Technologies Austria Ag Herstellungsverfahren zum Erzeugen einer Halbleitervorrichtung
CN107437548B (zh) * 2016-05-26 2020-03-10 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法、电子装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4513397A (en) * 1982-12-10 1985-04-23 Rca Corporation Electrically alterable, nonvolatile floating gate memory device
US4558339A (en) * 1982-03-09 1985-12-10 Rca Corporation Electrically alterable, nonvolatile floating gate memory device
JPS61222175A (ja) * 1985-03-01 1986-10-02 Fujitsu Ltd 半導体記憶装置の製造方法
JP2547622B2 (ja) * 1988-08-26 1996-10-23 三菱電機株式会社 不揮発性半導体記憶装置
JPH05190809A (ja) * 1992-01-14 1993-07-30 Kawasaki Steel Corp 半導体装置の製造方法
US5236853A (en) * 1992-02-21 1993-08-17 United Microelectronics Corporation Self-aligned double density polysilicon lines for ROM and EPROM
US5225362A (en) * 1992-06-01 1993-07-06 National Semiconductor Corporation Method of manufacturing a full feature high density EEPROM cell with poly tunnel spacer
KR0150048B1 (ko) * 1994-12-23 1998-10-01 김주용 플래쉬 이이피롬 셀 및 그 제조방법
KR0166840B1 (ko) * 1995-05-12 1999-01-15 문정환 리세스 채널 구조를 갖는 반도체 소자 및 그의 제조방법
US5854501A (en) * 1995-11-20 1998-12-29 Micron Technology, Inc. Floating gate semiconductor device having a portion formed with a recess
DE69630864T2 (de) * 1996-01-31 2004-11-04 Sgs-Thomson Microelectronics S.R.L., Agrate Brianza Verfahren zur Herstellung nichtflüchtiger Speicheranordnungen mit Tunneloxid
US5750428A (en) * 1996-09-27 1998-05-12 United Microelectronics Corp. Self-aligned non-volatile process with differentially grown gate oxide thickness
US5786614A (en) * 1997-04-08 1998-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Separated floating gate for EEPROM application

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9711483A2 *

Also Published As

Publication number Publication date
KR19990044687A (ko) 1999-06-25
US6027972A (en) 2000-02-22
DE19534780A1 (de) 1997-03-20
WO1997011483A3 (fr) 1997-06-12
WO1997011483A2 (fr) 1997-03-27
CN1202981A (zh) 1998-12-23
JPH11512568A (ja) 1999-10-26
RU2168797C2 (ru) 2001-06-10

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